UCIe MTP Interleaving Across Chiplets Without Reordering Buffers

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Solution Overview

Problem

Existing System on Chip (SoC) packages face challenges in efficiently managing and maintaining ordering of Management Transport Packets (MTPs) across multiple interconnected dies using Universal Chiplet Interconnect Express (UCIe) links, particularly when packets are transmitted in parallel over multiple sideband and mainband links, which often require complex reordering buffers and software that not all chiplets can afford.

Innovation Solution

A hardware-based MTP transportation mechanism that maintains management network ordering by using dedicated receive queues and predefined interleaving schemes for MTPs across multiple UCIe links, eliminating the need for memory reordering buffers and complex software reordering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex reordering buffers and software are used to maintain MTP ordering across multiple UCIe links, then ordering reliability is improved, but device complexity and resource requirements increase

Engineering Contradiction:

ImproveMTP ordering reliabilityVSAvoidreordering buffer complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments MTP transmission into multiple parallel paths (sideband and mainband links) while maintaining ordering through separate receive queues for each link type. By dividing the reordering function into link-specific queues rather than a single complex buffer, the system achieves reliable ordering across parallel links without requiring one large complex reordering structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary classification of incoming MTPs into sideband and mainband receive queues based on their arrival path before reordering is needed. This preliminary sorting action simplifies the subsequent reordering process by pre-organizing packets according to their transmission link, reducing the complexity of the final reordering operation.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If memory reordering buffers are implemented to ensure MTP ordering, then ordering accuracy is improved, but storage overhead increases

Engineering Contradiction:

Improveordering accuracyVSAvoidstorage overhead

Core Design Contradiction:

Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent implements separate receive queues with specific characteristics for different link types (sideband vs. mainband). Each queue is optimized for its specific link's timing and ordering properties, allowing accurate reordering without requiring excessive buffer space. This localized optimization achieves high ordering accuracy with minimal storage overhead compared to a universal buffer approach.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If software-based reordering is used for MTPs, then flexibility is improved, but processing time and productivity are reduced

Engineering Contradiction:

Improvereordering flexibilityVSAvoidMTP processing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces software-based reordering with a hardware-based mechanism using dedicated receive queues and interleaving schemes. The hardware automatically performs the reordering function through circuit-level logic rather than software execution, eliminating the performance penalty of software processing while maintaining the flexibility needed for different MTP ordering scenarios.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP4672008A1Apparatus, system, and method of communicating management transport packets over a universal chiplet interconnect express link

Publication Date: 2025.12.31 INTEL CORP

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AI summary

For example, an Integrated Circuit, e.g., a chiplet, may include Physical layer (PHY) circuitry to communicate with another IC, e.g., chiplet, over a Universal Chiplet Interconnect Express (UCIe) link. For example, the IC may include a System on Chip (SoC) bridge, which may be configured to transport a plurality of Management Transport Packets (MTPs) over a plurality of connection links of the UCIe link. For example, the SoC bridge may be configured to transport the plurality of MTPs according to a predefined interleaving scheme. For example, the predefined interleaving scheme may define a predefined order of assignment of a plurality of credit-path MTPs to a plurality of Receive (Rx) Queue Identifiers (RxQ-IDs) corresponding to the plurality of connection links.