UDIMM ECC Layout for 32-Bit Random Error Correction
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Solution Overview
Problem
Conventional unbuffered dual in-line memory modules (UDIMMs) are limited in their ability to correct multi-bit errors or random bit errors due to a limited number of data lines, which restricts their error correction capabilities to single bit errors only.
Innovation Solution
A memory system comprising a memory module with multiple memory devices and an ECC engine that corrects 32-random bit errors by using an ECC scheme, where each memory device is connected through multiple data lines, allowing for the detection and correction of errors across specific ranges, thereby enhancing error correction capabilities beyond single bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional UDIMM with limited data lines is used, then device complexity is reduced, but error correction capability is limited to single bit errors only
Solution Approach 1:
The memory module is divided into multiple memory devices (first, second, third, and fourth memory devices), each handling specific data lines. This segmentation allows the system to achieve enhanced error correction capability by distributing data across multiple devices while maintaining compatibility with the UDIMM form factor's data line constraints.
Solution Approach 2:
The memory module design enables multi-functionality by supporting both conventional single bit error correction and advanced 32-random bit error correction within the same UDIMM form factor. The system can operate in different error correction modes depending on the configuration, making it universally applicable to various reliability requirements.
2Reliability
If more data lines are added to improve error correction capability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a single-dimension approach (adding more data lines) to a multi-dimensional approach by organizing memory devices in a structured configuration where four memory devices share eight data lines. This dimensional reorganization enables 32-random bit error correction capability without increasing the physical data line count, thereby maintaining UDIMM form factor compatibility while enhancing reliability.
Data Source
AI summary
A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.