UE Data Processing Parallel Header Payload Paths
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Solution Overview
Problem
Conventional User Equipment (UE) structures face bottlenecks in high-speed data communication due to external memory access speed limitations and CPU performance constraints, particularly in achieving data transmission rates above 50 Mbps, where external memory access times are significantly longer than internal memory access times and CPU processing capacity is insufficient to handle increased data rates.
Innovation Solution
The UE apparatus includes internal and external memories interconnected by a bus device, with data divided into header and payload components processed independently through separate paths, utilizing embedded DMA blocks and alignment blocks to minimize external memory access and maximize parallel processing, allowing CPU and payload data processes to occur in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted at high speed above 50 Mbps, then data throughput is improved, but external memory access time becomes a bottleneck
Solution Approach 1:
The patent divides data into header and payload components, routing them through different processing paths. Header data is processed by the CPU while payload data is handled by embedded DMA blocks, enabling parallel processing and reducing the impact of external memory access limitations on overall throughput.
Solution Approach 2:
The patent introduces embedded DMA (Direct Memory Access) blocks as intermediary components between the external memory and the processing units. These DMA blocks can independently access and process payload data without requiring CPU intervention, thereby reducing the bottleneck effect of external memory access time.
2Productivity
If CPU processes all data sequentially, then processing accuracy is maintained, but processing speed becomes insufficient for high data rates
Solution Approach 1:
The patent segments the data processing function into two independent paths: one for header data processed by the CPU and another for payload data processed by embedded DMA blocks. This segmentation enables parallel processing, significantly improving processing speed while maintaining accuracy through dedicated processing units for each data type.
Solution Approach 2:
The embedded DMA blocks are designed to autonomously handle payload data processing without requiring continuous CPU intervention. They can independently access external memory, process data according to predefined protocols, and manage their own operations, thereby reducing CPU load and enabling faster overall processing.
3Productivity
If all data paths use external memory, then device complexity is reduced, but data transmission rate cannot exceed 50 Mbps
Solution Approach 1:
The patent creates separate data paths for header and payload data. The header path accesses external memory through the CPU, while the payload path uses embedded DMA blocks with direct external memory access capability. This segmentation enables higher data transmission rates by allowing simultaneous access to external memory through multiple independent channels.
Solution Approach 2:
The patent adds a new dimension to the memory access architecture by introducing embedded DMA blocks that provide a parallel access path to external memory. This transforms the single-dimensional CPU-centric access model into a multi-dimensional architecture where multiple processing units can simultaneously access external memory, thereby increasing data transmission rate.
Data Source
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AI summary
Provided is a method and an apparatus for processing data at a high speed by a UE for data communication. In the method, received data is divided into a header and payload information, which are then stored in different memories. In the method, header processing and payload data processing can be performed in parallel, and two memory devices can perform parallel processing without sharing a bus.