UEFI Multi-Core Reallocation for Boot Task Continuity
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Solution Overview
Problem
Existing Unified Extensible Firmware Interface (UEFI) programs suspend during execution, leading to unresponsiveness and the need for device restarts, which disrupt user experience and compromise log analysis.
Innovation Solution
A method and device that reallocates UEFI function codes across multiple cores in a processor to prevent unresponsiveness, using a first core to allocate and manage execution on a second core, and upon abnormality, reallocating to a third core, ensuring continuous operation and log preservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a UEFI program is suspended during execution on a single core, then the application stops responding and device restart is required, but this negatively affects user experience and causes loss of execution logs
Solution Approach 1:
The patent segments the UEFI execution environment by introducing multiple processor cores, where the first core handles UEFI application execution and the second core handles abnormality detection. This segmentation allows the system to monitor and respond to errors without requiring a full device restart, thus maintaining execution continuity while preserving user experience.
Solution Approach 2:
The patent introduces an intermediary mechanism (the second core acting as a monitor) that detects abnormalities in the UEFI program execution on the first core. This intermediary enables error detection and handling without interrupting the overall boot process, allowing logs to be preserved and analyzed without device restart.
2Loss of information
If device restart is performed to collect UEFI program execution log, then log analysis becomes possible, but execution log may not be saved and user experience deteriorates
Solution Approach 1:
The patent implements preliminary action by having the second core continuously monitor the first core's execution status during the UEFI boot process. Abnormality detection and log preservation are performed in advance before the error can cause system failure, eliminating the need for post-error log collection through device restart.
Solution Approach 2:
The patent establishes a feedback mechanism where the second core continuously monitors the execution state of the first core and provides real-time abnormality detection. This feedback loop enables immediate error detection and log preservation without requiring system restart, thus preventing information loss and reducing time delays.
3Productivity
If multi-threaded execution is supported in UEFI, then program responsiveness is improved, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the processor into multiple cores with specific functional assignments: the first core executes UEFI applications while the second core monitors for abnormalities. This segmentation enables concurrent execution and monitoring, improving productivity without requiring complex multi-threading implementation across the entire UEFI architecture.
Solution Approach 2:
The patent implements local quality by assigning different functional characteristics to different cores: the first core is optimized for UEFI application execution while the second core is optimized for abnormality detection. This localized functional differentiation enables improved execution efficiency without uniformly increasing complexity across the entire system.
Data Source
AI summary
A program execution method includes: during a Unified Extensible Firmware Interface (UEFI) boot process, determining a core in a processor that executes a UEFI application as a first core; using the first core to allocate a first function code in the UEFI application to a second core in the processor for execution, the first core being different from the second core, the first function code being code for executing a UEFI boot task; and in response to an abnormality in the second core, using the first core to allocate the first function code to a third core in the processor for execution, the third core being different from the first and second cores.