Caching UEFI Instructions in Non-Volatile Memory for Fast Boot
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Solution Overview
Problem
Current Information Handling Systems (IHS) face challenges in reducing BIOS and UEFI boot times due to slow accesses through the BIOS' serial peripheral interface (SPI) over a low pin count (LPC) bus, memory configuration, and retrieval of instructions from peripheral devices, leading to prolonged boot times, especially in systems with increased system memory and I/O configurations.
Innovation Solution
Implementing a system and method to cache UEFI and other firmware instructions in a non-volatile memory, such as a NVDIMM, allowing the processor to copy and load instructions directly from the non-volatile memory during a fast boot mode, bypassing slow accesses to the UEFI chipset and peripheral devices, and utilizing a reset vector to point to the cached instructions in the non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If instructions are loaded from UEFI chipset through SPI over LPC bus, then system reliability is maintained, but boot time increases significantly
Solution Approach 1:
The patent applies preliminary action by copying UEFI instructions from the UEFI chipset to non-volatile memory during system initialization or manufacturing. This pre-positioning of instructions allows the processor to load them directly from non-volatile memory during boot operations, eliminating the need for slow SPI/LPC bus accesses and significantly reducing boot time while maintaining access reliability.
Solution Approach 2:
The patent introduces non-volatile memory as an intermediary between the UEFI chipset and the processor. This intermediary stores copies of UEFI instructions, allowing the processor to access them directly without going through the slow SPI interface over the LPC bus. The non-volatile memory acts as a buffer that decouples the fast processor from the slow firmware interface, resolving the speed-time contradiction.
2Loss of time
If memory configuration and peripheral device retrieval are performed during boot, then system reliability is ensured, but boot time is prolonged
Solution Approach 1:
The patent extracts the instruction loading operation from the complex boot sequence that involves memory configuration and peripheral device retrieval. By loading instructions directly from non-volatile memory, the system separates the critical instruction acquisition step from the slower, more complex initialization processes, thereby reducing overall boot time while maintaining necessary configuration steps.
Data Source
AI summary
Systems and methods for caching firmware instructions in a non-volatile memory of an information handling system (IHS). In an illustrative, non-limiting embodiment, an IHS may include a processor, a non-volatile memory coupled to the processor, and a unified extensible firmware interface (UEFI) chipset coupled to the processor. The processor may be configured to: copy instructions stored in the UEFI chipset to the non-volatile memory prior to a reboot or restart of the HIS, and, at least in part in response to the reboot or restart operation, load at least a subset of the instructions directly from the non-volatile memory rather than from the UEFI chipset as part of a fast boot mode of operation.