UFS SLC Cache Partitioning for High-Bandwidth Write Performance

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Solution Overview

Problem

Existing data storage methods face performance degradation due to insufficient space in the SLC cache for high-bandwidth data writes, leading to inefficient use of the cache and reduced write performance in storage devices.

Innovation Solution

A data storage method that divides the SLC cache into different areas based on data response levels, ensuring high-speed data is stored in specific areas and low-speed data is managed to maintain cache space for high-bandwidth writes, using a pinning stream manager to determine optimal storage locations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all data is written to the SLC cache using Turbo Write technology, then write performance is improved, but the cache space becomes insufficient for high-bandwidth data writes

Engineering Contradiction:
Improvewrite performanceVSAvoidcache space
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The SLC cache is segmented into multiple areas (first area, second area, third area) with different data response levels. This segmentation allows the system to differentiate between high-bandwidth data requiring immediate cache storage and low-bandwidth data that can be stored in slower memory, thereby preserving sufficient cache space for performance-critical operations while still utilizing the cache for acceleration where appropriate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different areas of the SLC cache are assigned different qualities based on data response levels. The first area (high response level) prioritizes fast access for critical data, the second area (medium response level) provides balanced performance, and the third area (low response level) accepts slower access in exchange for preserving cache space. This local quality differentiation resolves the contradiction by optimizing cache utilization according to specific data requirements rather than treating all cache space uniformly.

Inventive Principle:
Principle #3Local quality

2Speed

If the SLC cache is used as a buffer for all data, then write speed is enhanced, but data access time increases for data that does not require high bandwidth

Engineering Contradiction:
Improvewrite speedVSAvoiddata access time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The cache is divided into multiple areas with different response levels, allowing the system to segment data access patterns. High-bandwidth data is directed to the first area for fast write and read operations, while low-bandwidth data is directed to the second or third areas where slower access is acceptable. This segmentation eliminates unnecessary fast access overhead for data that does not require it, reducing overall system latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically determines the data response level and selects appropriate cache areas based on the specific data characteristics and access patterns. This dynamic adaptation allows the system to optimize between write speed and access time in real-time, adjusting the storage location according to the actual needs of each data operation rather than using a static caching strategy.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260104814A1Data storage method and device
Publication Date: 2026.04.16 SAMSUNG ELECTRONICS CO LTD
  • US20260104814A1 patent drawing
  • US20260104814A1 patent drawing
  • US20260104814A1 patent drawing

AI summary

A data storage includes: determining, in response to receiving an IO request, a data response level for the IO request; determining, according to the data response level, a storage area for storing data to be written corresponding to the IO request in a UFS device, the UFS device comprises a high speed buffer and a normal storage area; and writing the data to be written into the determined storage area, wherein the high speed buffer comprises a first area, a second area, and a third area, and the UFS device is configured block data stored in the third area is from being flushed into the normal storage area. The speeds of the high speed buffer are greater than the speeds of the normal storage area. The first area, the second area, and the third area and the normal storage area correspond to different data response levels, respectively.