UFS Flash Memory Cell Reconfiguration for Endurance

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Solution Overview

Problem

Components of universal flash storage (UFS) devices, including single-level cells and triple-level cells, have limited lifespans due to wear from repeated use, leading to non-functional cells that reduce the capabilities and operation of UFS devices.

Innovation Solution

The method involves configuring degraded triple-level cells (TLCs) as single-level cells (SLCs) based on a degradation attribute, allowing these cells to remain functional as SLCs even if they are not functional as TLCs. This process maintains the capacity of writebooster buffers and non-volatile memory by accurately identifying and reconfiguring degraded cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If triple-level cells (TLCs) are used to maximize storage capacity, then the storage density is improved, but the endurance and reliability deteriorate due to limited lifespan from repeated use

Engineering Contradiction:
Improvestorage capacityVSAvoidendurance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the operational parameters of flash memory cells by transitioning from TLC mode to SLC mode when degradation is detected. This parameter change allows the same physical cells to continue functioning with different characteristics, maintaining reliability while preserving storage capacity through reconfiguration

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system dynamically adjusts the operational mode of flash memory cells based on their degradation state. Cells that have worn beyond TLC thresholds are automatically reconfigured as SLCs, creating a dynamic adaptation mechanism that responds to changing cell conditions to maintain overall system reliability

Inventive Principle:
Principle #15Dynamics

2Reliability

If degraded TLCs are retired to maintain reliability, then the reliability is improved, but the storage capacity and productivity deteriorate

Engineering Contradiction:
Improvefunctional reliabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of permanently retiring degraded cells, the patent recovers their utility by reconfiguring them as SLCs. This allows the system to discard cells from their original TLC function while recovering their value through alternative SLC usage, thereby maintaining both reliability and storage capacity

Inventive Principle:
Principle #34Discarding and recovering

Solution Approach 2:

The patent makes flash memory cells universal by enabling them to function in multiple modes (TLC and SLC). This multi-functionality allows degraded cells to be reassigned to different operational roles, ensuring that no storage capacity is permanently lost and productivity is maintained through flexible resource allocation

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If the number of program/erase cycles is increased to utilize more cells, then the storage capacity is improved, but the cell degradation accelerates and reliability worsens

Engineering Contradiction:
Improvestorage capacityVSAvoidcell lifespan
Core Design Contradiction:
Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The system performs preliminary monitoring of cell degradation through read-disturb attributes and program/erase cycle counting. By detecting degradation early, the system can proactively reconfigure cells before they fail, extending their useful lifespan and maintaining storage capacity over longer durations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12265711B1Mechanism to enhance endurance in universal flash storage devices
Publication Date: 2025.04.01 QUALCOMM INC
  • US12265711B1 patent drawing
  • US12265711B1 patent drawing
  • US12265711B1 patent drawing

AI summary

Methods that may be performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells. Various embodiments may include setting a number of degraded triple-level cells (TLCs) attribute, and configuring at least one degraded TLC as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC. Some embodiments may include identifying the at least one degraded TLC based on at least one degradation attribute associated with the at least one degraded TLC, the at least one degradation attribute configured to indicate that the at least one degraded TLC is not functional as a TLC, and identifying an amount of degraded TLCs that are not functional as a TLC.