UFS Host Controller Register Logic for Data Integrity
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Solution Overview
Problem
The implementation of the UFSHCI standard in a host compliant with both the UFS and UFSHCI standards can lead to issues such as halted read/write operations or data corruption in flash memory devices, due to contradictions in the Run-Stop register and Door bell register states during data transfer.
Innovation Solution
Incorporating a semiconductor device with a UFS host controller that includes a Run-Stop register, a Door bell register, and a ready bit to manage data transfer states, ensuring that the next transfer is not initiated until the previous one is completed, thereby preventing data corruption and operation halts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Run-Stop register is cleared to stop data transfer processing, then the host controller can be halted, but data corruption or operation halts may occur if the Door bell register is still set
Solution Approach 1:
The host controller continuously monitors the state of the Door bell register and uses this feedback to determine whether it is safe to clear the Run-Stop register. The controller checks if the Door bell register is set before proceeding with transfer stop operations, and only clears Run-Stop when confirmed that no new transfers are pending, thus preventing data corruption while maintaining reliable control
Solution Approach 2:
Before clearing the Run-Stop register to halt data transfer, the host controller performs a preliminary check of the Door bell register state. This preliminary action ensures that no new transfer requests are pending, preventing the scenario where clearing Run-Stop mid-transfer would cause data corruption or operation halts
2Productivity
If the host controller allows continuous transfer registration, then productivity is improved, but data corruption occurs when Run-Stop is cleared during active transfer
Solution Approach 1:
The host controller dynamically adjusts its acceptance of new transfer requests based on the current transfer state. When a transfer is detected as in-progress (Run-Stop cleared while Door bell set), the controller dynamically blocks new transfer registrations. This dynamic control allows continuous operation during normal transfers while preventing data corruption during state transitions
Solution Approach 2:
The controller uses feedback from the Door bell register and Run-Stop register states to dynamically control whether new transfers can be registered. The feedback mechanism detects when Run-Stop is cleared during active transfer and prevents subsequent transfer registrations until the current transfer completes, maintaining both productivity and data integrity
3Reliability
If the host controller checks transfer state before clearing Run-Stop, then data integrity is maintained, but operation time increases due to additional checks
Solution Approach 1:
The host controller performs a preliminary check of the Door bell register state before clearing the Run-Stop register. This single preliminary check ensures data integrity by confirming no new transfers are pending, while minimizing time loss by performing only one essential check rather than continuous monitoring or multiple verification steps
Data Source
AI summary
When contents of UFSHCI standard are directly implemented in a UFS host, a problem may occur such that read/write operations of a UFS device stop or contents of data are destroyed. A semiconductor device has a UFS host controller that performs data transfer with a universal flash storage (UFS) device. The semiconductor device includes a Run-Stop register that sets the UFS host controller into a processing possible state, a Door bell register that instructs the UFS host controller to perform transfer, and a ready bit that indicates whether or not the UFS host controller can perform processing of transfer request. When the Run-Stop register is cleared while the data transfer is in process, the UFS host controller prevents a next data transfer from being registered until the data transfer is completed.