UFS Memory Self-Test via Internal Loop-Back Signal Verification
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Solution Overview
Problem
Existing methods for testing universal flash storage (UFS) interfaces are costly and fail to adapt quickly to changing technologies, necessitating a more efficient and cost-effective approach for ensuring normal operation of UFS link and physical layers.
Innovation Solution
A self-test method for UFS interfaces is implemented, utilizing a test unit within the memory device to generate and transmit signals through the UFS link and physical layers, allowing for loop-back and arbitration to verify proper operation, including lane control and data transmission, without the need for external testing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external testing devices are used to test UFS interface, then testing reliability is improved, but testing cost increases
Solution Approach 1:
The memory device performs self-testing by generating test signals internally and using its own transmitting and receiving units to verify UFS interface operation. The test unit within the memory device sends signals through the UFS link layer and physical layer, then receives echoed signals back, eliminating the need for external testing devices and reducing testing costs while maintaining reliability.
Solution Approach 2:
The patent introduces a loop-back line as an intermediary component that redirects test signals from the receiving unit back to the transmitting unit. This intermediary mechanism enables the memory device to test its own interface by creating a closed signal path, allowing self-verification without external equipment.
2Measurement precision
If comprehensive UFS interface testing is performed, then testing accuracy is improved, but testing time increases
Solution Approach 1:
The test unit performs preliminary testing by sending test signals through the UFS link layer and physical layer before actual data transmission occurs. This preliminary action verifies the integrity of signal transmission paths in advance, ensuring accurate testing of interface operation without requiring time-consuming comprehensive tests during normal operation.
Solution Approach 2:
The patent implements a feedback mechanism where the receiving unit receives test signals and echoes them back to the transmitting unit through the loop-back line. The test unit then compares the original and returned signals to verify interface operation accuracy, enabling rapid testing through efficient feedback-based verification.
Data Source
AI summary
A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.