Variable Gain Attenuator for UHF RFID Signal Detection
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Solution Overview
Problem
Existing RFID data detectors face challenges in handling large RF signals, interpreting small RF signals, and high power consumption, leading to inefficient data detection across various operating conditions.
Innovation Solution
The implementation of a method involving a variable gain attenuator and a programmable offset voltage in the data path of the RFID transponder, which includes a single stage rectifier and a data slicer, to handle varying RF signal levels and reduce power consumption through a preamplifier and dynamic latch combination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full wave rectifier circuit is used to detect RF signals, then the circuit can handle RF signals within a certain voltage range, but it cannot handle large RF signals that exceed the supply voltage range
Solution Approach 1:
The patent applies dynamics by making the gain of the amplifier variable rather than fixed. The amplifier's gain is dynamically adjusted based on the input signal level, allowing the circuit to adapt to both small and large RF signals. This is achieved through a control mechanism that modifies the amplifier's operation in response to signal conditions, enabling reliable data detection across a wide dynamic range of RF signal strengths
Solution Approach 2:
The patent changes the parameter of amplifier gain from a fixed value to a variable parameter. By controlling the gain parameter to vary with input signal level, the circuit can process both weak and strong RF signals effectively. This parameter change allows the same circuit topology to handle a broad range of signal amplitudes without requiring multiple different circuit designs
2Measurement precision
If traditional data slicing is used with a latched comparator, then the circuit can interpret RF signals, but it struggles with small RF signals due to voltage excursions being too small for reliable comparison
Solution Approach 1:
The patent applies preliminary action by performing signal amplification and conditioning before the data slicing operation. The amplifier prepares the RF signal by increasing its amplitude to a level suitable for reliable comparison by the latched comparator. This preliminary amplification ensures that even small RF signals produce sufficient voltage excursions for accurate data interpretation, while the amplifier is designed to consume minimal power in the process
3Adaptability or versatility
If the rectifier stage operates as a voltage doubler to handle varying signal levels, then large signals can be processed, but the voltage excursion at the data slicer input exceeds the supply voltage
Solution Approach 1:
The patent introduces an intermediary amplifier stage between the rectifier and the data slicer. This amplifier acts as a mediator that receives the potentially excessive voltage from the rectifier stage and conditions it to appropriate levels for the data slicer. The amplifier buffers and scales the voltage, preventing overload damage to the data slicer while maintaining the ability to process both small and large input signals
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the detection of RF signals across a wide range of strengths, improves low-level signal interpretation, and decreases power consumption, thereby improving overall data detection efficiency and reliability.
Implementation Method 1
The full wave rectifier circuit rectifies an RF input signal having −Vp to +Vp voltage excursion. The rectified voltage is then converted to a digital signal by a data slicer.
Implementation Method 2
At −Vp, diode 902 charges capacitor 900 to Vp−Vd as shown. Then at +Vp, diode 906 charges capacitor 908 to Vp−Vd.
Data Source
AI summary
A method of detecting a signal in radio frequency identification (RFID) transponder (FIG. 1) is disclosed. The method includes receiving a signal (FIG. 7) having a first time in a first logic state (high) and having a second time in a second logic state (low). A weight (700, 702) is determined in response to the first time and the second time. An output signal (from A2D) is produced in response to the weight and one of the first and second logic states.