Ultra High Voltage ESD Diode Current Gain Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Common electrostatic discharge (ESD) Diodes limit current gain during cathode to anode positive bias operations in ultra high voltage applications, as the P/N junction is biased, restricting current increase beyond 800 V.
Innovation Solution
A semiconductor device with a specific layered structure, including N+ and P+ regions, is designed to enhance current gain by modifying the P/N junction, allowing increased current and negative resistance at higher voltages through the inclusion of a buried semiconductor region and additional doping layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional ESD Diode with P/N junction is used, then the device structure is simple, but the current gain is limited during cathode to anode positive bias operation at ultra high voltage
Solution Approach 1:
The device is segmented into multiple functional regions including a first semiconductor region, second semiconductor region, third semiconductor region, fourth semiconductor region, and fifth semiconductor region. Each region serves a specific function in enabling current gain during cathode to anode positive bias operation, resolving the contradiction by dividing the device into specialized segments rather than using a simple P/N junction structure.
Solution Approach 2:
The invention transitions from a conventional two-region P/N junction to a five-region layered structure with alternating conductivity types. This dimensional expansion in structural complexity enables new operational modes including cathode to anode positive bias operation with current gain, directly addressing the limitation of conventional ESD diodes.
2Temperature
If the P/N junction is biased in conventional ESD Diodes, then the device operates at ultra high voltage, but the current increase is restricted beyond 800 V
Solution Approach 1:
Different semiconductor regions are doped with specific conductivity types (n-type or p-type) to create localized functional zones. The fourth and fifth regions are specifically configured to enable current gain during cathode to anode positive bias operation, allowing the device to sustain current increase beyond 800 V while maintaining ultra high voltage operation capability.
Solution Approach 2:
The device uses a composite structure of five different semiconductor regions with alternating conductivity types. This composite architecture combines the benefits of each region to achieve both ultra high voltage operation and enhanced current gain, overcoming the limitation of conventional single-structure ESD diodes.
3Productivity
If additional semiconductor regions and doping layers are added to enhance current gain, then current gain and negative resistance increase, but the device complexity increases
Solution Approach 1:
Multiple semiconductor regions are merged into a single integrated device structure with alternating conductivity types. The first through fifth regions are combined to work together in enabling cathode to anode positive bias operation with current gain, achieving enhanced functionality while maintaining a unified device architecture.
Solution Approach 2:
The five-region structure serves multiple functions simultaneously: it enables ultra high voltage operation, provides current gain during cathode to anode positive bias operation, and generates negative resistance. This multi-functionality justifies the increased structural complexity by delivering multiple performance benefits from a single device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves higher current gain and negative resistance at ultra high voltages, sustaining current beyond the limitations of conventional ESD Diodes, with significant increases above the trigger voltage.
Implementation Method 1
the fifth semiconductor region is configured to cause an increase in a current during a cathode to anode positive bias operation
Implementation Method 2
Common ESD Diodes sometimes achieve some current gain in a cathode to anode positive bias operation for ultra high voltage applications
Data Source
AI summary
A semiconductor device includes a semiconductor substrate. A first semiconductor region is over a portion of the semiconductor substrate to a first depth. A second semiconductor region is in the first semiconductor region. A third semiconductor region is in the first semiconductor region. A fourth semiconductor region is outside the first semiconductor region. A fifth semiconductor region is outside the first semiconductor region to a fifth depth, the fifth semiconductor region being adjacent the fourth semiconductor region. A sixth semiconductor region is below the fifth semiconductor region and to a sixth depth. The sixth depth is equal to the first depth. A first electrode is connected to the third semiconductor region. A second electrode is connected to the fourth and fifth semiconductor regions. The fifth semiconductor region is configured to cause an increase in a current during a cathode to anode positive bias operation between the first and second electrodes.