UL-OFDMA Deinterleaver Segmentation for Latency Reduction

The single shared deinterleaver is segmented into multiple parallel deinterleavers (first deinterleaver and second deinterleaver). Each deinterleaver can independently process different RUs simultaneously, eliminating the sequential processing bottleneck while maintaining manageable hardware complexity through modular replication.

Multiple deinterleavers are merged into a unified processing architecture with a common buffer memory system. The buffers associated with each deinterleaver are coordinated to work together, allowing simultaneous processing of multiple RUs while sharing common resources like the buffer memory management logic.

Instead of increasing the memory dimension of a single deinterleaver, the solution adds a temporal dimension by introducing multiple parallel deinterleavers that can simultaneously process different RUs. The buffer memory is dynamically allocated across multiple processing units, effectively increasing processing capability without proportionally increasing total memory capacity.

The buffer allocation is made dynamic, where buffers associated with each deinterleaver can be flexibly assigned and reassigned based on the current processing needs. This dynamic allocation allows the system to handle variable RU sizes efficiently without requiring static over-provisioning of memory capacity.

The workload of processing varying-sized RUs is segmented across multiple parallel deinterleavers. Each deinterleaver receives a portion of the RUs and processes them independently, allowing smaller RUs to be processed without waiting for larger RUs to complete, thus maintaining adaptability while improving efficiency.

The parallel deinterleaver architecture enables continuous useful action by ensuring that while one deinterleaver is processing an RU, other deinterleavers are simultaneously processing other RUs. This eliminates idle waiting time and maintains continuous productive operation across the system.