ULk Dielectric Layer Protection in Semiconductor Interconnect Fabrication
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Solution Overview
Problem
Low-k dielectric materials in semiconductor devices are susceptible to damage during processing steps like etching, wet-cleaning, and chemical mechanical planarization, leading to increased dielectric constant and degraded performance.
Innovation Solution
A method involving the formation of an ultra-low-k dielectric layer with a hard mask, followed by selective etching and planarization to minimize damage, where the top surface of the ULK dielectric layer is lower than the conductive layer, and a cap layer is applied to protect the ULK dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional damascene processing steps (etching, wet-cleaning, CMP) are used to fabricate metal interconnections, then interconnect structures can be formed, but the low-k dielectric materials suffer damage leading to increased dielectric constant
Solution Approach 1:
The patent applies preliminary action by performing planarization of the low-k dielectric layer before the damaging CMP process on metal layers. This sequence ensures the low-k layer is planarized while still protected, and subsequent CMP on metal layers does not expose the low-k layer to damaging conditions. The hard mask is also removed selectively after metal filling, preventing unnecessary exposure of the low-k layer to etching and cleaning processes.
Solution Approach 2:
The patent uses the hard mask as an intermediary protective layer during the fabrication process. The hard mask remains in place to protect the low-k dielectric layer from damage during metal layer deposition and CMP processes. The hard mask is selectively removed only after metal filling is complete, serving as a temporary but essential mediator that shields the sensitive low-k material from harmful processing conditions.
2Ease of manufacture
If multiple processing steps (etching, wet-cleaning, CMP) are performed on low-k dielectric layers, then metal interconnections can be fabricated, but the low-k materials become damaged and their dielectric constant increases
Solution Approach 1:
The patent performs preliminary planarization of the low-k dielectric layer using CMP before subsequent metal layer processing. This preliminary action completes the necessary planarization while the low-k layer is still protected by the hard mask, avoiding the need for additional CMP steps that would expose the low-k layer to damaging conditions during metal interconnection fabrication.
Solution Approach 2:
The hard mask serves as an intermediary protective barrier throughout the fabrication process. It allows metal layers to be deposited and planarized via CMP without directly exposing the low-k dielectric layer to these harmful processes. The hard mask is removed selectively only after metal filling is complete, minimizing the low-k layer's exposure to harmful factors while maintaining ease of manufacture.
3Ease of operation
If the hard mask is removed early in the process, then the low-k dielectric layer is exposed, but it becomes susceptible to damage from subsequent processing steps
Solution Approach 1:
The patent performs all necessary planarization of the low-k dielectric layer as a preliminary action before removing the hard mask. This ensures the low-k layer achieves its required flatness while still protected, and subsequent steps can proceed with the hard mask in place, preventing early exposure and vulnerability to damage from processing steps.
Solution Approach 2:
The hard mask remains as an intermediary protective layer throughout critical processing steps. It maintains ease of operation by allowing subsequent metal layer deposition and planarization to proceed without direct exposure of the low-k layer. The hard mask is removed only after all necessary processing is complete, at which point the low-k layer is already planarized and protected from further damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to low-k dielectric materials, maintaining their low dielectric constant and enhancing the overall performance of semiconductor devices by preventing capacitive coupling and RC delay.
Implementation Method 1
planarizing the conductive layer
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an ultra low-k (ULK) dielectric layer on the substrate; forming a hard mask on the ULK dielectric layer; forming an opening in the hard mask and the ULK dielectric layer; forming a conductive layer in the opening and on the hard mask; planarizing the conductive layer; and removing the hard mask to expose the ULK dielectric layer so that the top surface of the ULK dielectric layer is lower than the top surface of the conductive layer.