Ultra-dense 3D Transistor Design via Vertical Stacking
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistors to single-digit nanometer nodes, particularly in transitioning from two-dimensional to three-dimensional circuits, as they struggle with increased complexity and the need for higher transistor density.
Innovation Solution
The method involves forming mandrels with perpendicular sidewalls over a substrate, creating channel layers and gate dielectric and electrode layers, and using multiple trenches to form stacked transistor pairs, allowing for ultra-dense 3D transistor design with semiconductive oxide integration and metal first integration, enabling vertical stacking without requiring epitaxially grown silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are scaled to single-digit nanometer nodes using conventional 2D fabrication, then transistor density per unit area increases, but fabrication complexity and difficulty increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical transistors by forming channel structures that extend in the vertical dimension. Multiple channels are stacked above each other, allowing density improvement without proportionally increasing fabrication complexity, as the vertical stacking uses similar process steps repeated in different layers.
Solution Approach 2:
The fabrication process is segmented into modular steps that can be repeated: forming mandrels, depositing channel material on sidewalls, forming gate structures, and creating source/drain regions. This segmentation allows the complex task of creating high-density 3D transistors to be broken into manageable, repeatable process modules.
2Quantity of substance
If vertical stacking of transistors is implemented, then transistor density increases, but process steps and fabrication difficulty increase
Solution Approach 1:
Multiple transistor channels are combined into a single vertical stack structure, sharing common source/drain regions and gate structures. This merging approach increases density while reducing the number of separate process steps compared to fabricating each transistor individually, as materials and structures are formed in bulk rather than separately for each device.
Solution Approach 2:
Mandrels are formed in advance as templates before the channel material is deposited on their sidewalls. This preliminary action establishes the vertical geometry and positioning of channels before subsequent processing steps, simplifying the overall fabrication sequence and improving efficiency by pre-defining the structure that will guide subsequent material deposition.
3Reliability
If conventional epitaxial growth methods are used for vertical transistor channels, then channel quality is maintained, but fabrication complexity and temperature requirements increase
Solution Approach 1:
The patent changes the material parameter from requiring epitaxially grown silicon to using semiconductive oxides that can be deposited using standard thin-film techniques. This parameter change maintains functional quality while dramatically simplifying fabrication, as the oxide materials can be formed at lower temperatures using ALD, CVD, or sputtering without requiring complex epitaxial equipment and processes.
Data Source
AI summary
A semiconductor device includes a substrate, a first wiring layer over the substrate, and a first array of transistor pairs extending over the first wiring layer. Cross sections of each transistor pair cut through the first array. The cross sections of each transistor pair have a similar structure. Each transistor pair includes a mandrel having two opposite sidewalls that are perpendicular to the substrate and extending along a direction of the first array of transistor pairs. Each transistor pair includes two transistors symmetrically disposed over the two opposite sidewalls of the respective mandrel.