Ultra-high-k Dielectric Capacitors Integrated in Package Substrates
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Solution Overview
Problem
Current semiconductor devices with discrete capacitors occupy large areas on the package substrate, increasing Z-height and assembly costs, and are challenging to miniaturize due to the need for high-temperature processing of ultra-high-k dielectric materials.
Innovation Solution
Integration of ultra-high-k dielectric capacitors directly into the package substrate using low-temperature organic substrates and additive manufacturing techniques, such as printing, to reduce Z-height and increase capacitance density without the need for separate assembly, allowing for reduced package thickness and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If discrete capacitors are attached to the package substrate, then capacitance is provided for power delivery, but the package area is occupied and Z-height increases
Solution Approach 1:
The patent merges the capacitor structure with the package substrate by integrating ultra-high-k dielectric layers directly into the substrate layers. The capacitors are formed as part of the substrate stack, combining what were previously separate discrete components and substrate into a unified integrated structure, thereby eliminating occupied package area while maintaining capacitance functionality.
Solution Approach 2:
The patent transitions from planar placement of discrete capacitors on the package substrate surface to vertical stacking of capacitor structures within the substrate layers. By utilizing the Z-dimension (thickness direction) through multi-layer construction, the patent achieves high capacitance density without occupying additional package area, effectively moving the solution from 2D to 3D space utilization.
2Quantity of substance
If discrete capacitors are attached to the package substrate, then capacitance is provided, but assembly operations and process time increase
Solution Approach 1:
The patent combines the capacitor fabrication process with the substrate manufacturing process. Ultra-high-k dielectric layers are deposited and processed together with the substrate layers in an integrated sequence, eliminating separate assembly operations for attaching discrete capacitors. This merging of processes reduces both assembly time and the number of manufacturing steps.
Solution Approach 2:
The capacitor structures are formed during the substrate fabrication process itself, before final assembly operations. The ultra-high-k dielectric layers are deposited and patterned as part of the substrate layer construction, preparing the capacitor structures in advance within the substrate, thereby eliminating subsequent assembly steps and reducing overall process time.
3Quantity of substance
If ultra-high-k dielectric materials are used for high capacitance density, then capacitance density increases, but processing temperature must be greater than 500 degrees C
Solution Approach 1:
The patent changes the temperature parameter of the processing conditions by developing and using ultra-high-k dielectric materials that can be deposited and annealed at temperatures below 500 degrees C. This parameter change enables the use of low-temperature substrates such as organic substrates while still achieving the necessary dielectric properties for high capacitance density through modified deposition and annealing processes.
Solution Approach 2:
The patent employs composite material structures combining ultra-high-k dielectric layers with low-temperature substrates. By creating a composite system where the dielectric materials are specifically engineered to be compatible with low-temperature processing, the patent achieves high capacitance density without requiring high-temperature substrates, enabling integration with organic and other temperature-sensitive materials.
4Area of stationary object
If discrete capacitors are miniaturized to sub-millimeter scales, then package area is reduced, but assembly becomes particularly challenging
Solution Approach 1:
The patent merges the capacitor structures with the substrate at the same miniaturized scale through integrated fabrication processes. Rather than attempting to assemble separate sub-millimeter discrete capacitors, the capacitor structures are formed directly within the substrate layers using the same lithography and deposition processes, eliminating the assembly challenges associated with handling and placing miniaturized components.
Solution Approach 2:
The patent replaces the mechanical assembly process (pick and place of discrete components) with a direct fabrication process where capacitor structures are formed in-situ within the substrate. This substitution of mechanical assembly with integrated manufacturing eliminates the difficulty of assembling sub-millimeter components while achieving the same area reduction benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces package thickness, eliminates the need for discrete capacitors on the land-side, decreases assembly time and costs, and enhances capacitance density while maintaining low parasitic resistance and inductance.
Implementation Method 1
capacitors with high capacitance densities (e.g., 10-10,000 nF/mm2), which requires ultra-high-k dielectric materials with relative permittivity of approximately 1,000-10,000
Data Source
AI summary
Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor that is integrated with a first organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes.