Ultra-Low Power Framework for Interrupt Alignment and Memory Prediction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing electronic devices with always-on coprocessors face increased power consumption due to frequent discrete wake-ups of the coprocessor and application processor, which are triggered by external interrupts and timer interrupts.

Innovation Solution

An ultra-low power framework is implemented, which includes an interrupt align and activity group, a memory predict monitor, and a task dynamic migration monitor. This framework aligns multiple interrupts to wake up the coprocessor only when necessary, predicts when global memories are accessed to power them off, and dynamically migrates tasks to optimize memory usage based on loading and frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the coprocessor is discretely woken up by external interrupts or timer interrupts to perform low-power functions, then the coprocessor can respond to user behaviors, but the frequent wake-ups increase power consumption

Engineering Contradiction:

Improveresponse capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple discrete interrupts (external interrupts and timer interrupts) into a single unified interrupt handling mechanism. The interrupt alignment unit merges these interrupt sources so that the coprocessor is woken up by one consolidated interrupt rather than multiple separate interrupts, reducing the frequency of wake-ups while maintaining the ability to respond to user behaviors.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements preliminary action by having the interrupt alignment unit pre-process and consolidate interrupts before they reach the coprocessor. By aligning and merging interrupts in advance, the system prepares the interrupt stream to minimize coprocessor wake-ups, ensuring that the coprocessor is only woken when necessary while still maintaining responsive behavior.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the application processor is activated for subsequent operations when the coprocessor determines wake-up is needed, then the application can continue processing, but the application processor's power consumption increases

Engineering Contradiction:

Improveprocessing capabilityVSAvoidapplication processor power consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges the interrupt handling responsibilities between the coprocessor and application processor. By implementing interrupt alignment, the system consolidates interrupt processing in the coprocessor whenever possible, reducing the need for application processor activation. This merging of processing responsibilities maintains productivity while reducing the application processor's power consumption.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of operation

If global memories are kept powered on to support coprocessor operations, then memory access is available, but power consumption increases when memories are not accessed

Engineering Contradiction:

Improvememory access availabilityVSAvoidglobal memory power consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management for global memories. The memory power control unit dynamically adjusts the power state of global memories based on actual access patterns and system state. Memories are powered on only when accessed and powered off when not needed, creating a dynamic system that adapts to varying operational requirements while optimizing power consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms to control global memory power states. The system monitors memory access patterns and uses this feedback information to make informed decisions about when to power memories on or off. This feedback-driven approach ensures that memories remain available when needed while minimizing power consumption during idle periods.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250044858A1Electronic device and method for interrupt processing with low power consumption

Publication Date: 2025.02.06 MEDIATEK SINGAPORE PTE LTD

AI summary

An electronic device includes a local memory, multiple global memories, a coprocessor, an application processor, a memory protect unit and a memory access monitor. The coprocessor is electrically coupled to the local memory, the global memories, and the application processor, and runs an ultra-low power framework. The ultra-low power framework includes an interrupt align and activity group, a memory predict monitor, and a task dynamic migration monitor. The interrupt align and activity group aligns multiple interrupts, so that the coprocessor is waken up based on the aligned interrupts to perform all expired low power functions, and the application processor is aligned to wake up based on a wakeup of the coprocessor. The memory protect unit and the memory access monitor are electrically coupled to the global memories and the coprocessor, run the memory predict monitor, and determine whether to power off the global memories through the memory access monitor.