Ultra-Short Standard Cell Layout With Pin Access Routing
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Solution Overview
Problem
The reduction in standard cell height in semiconductor technologies limits block-level area scaling due to poor routeability caused by a decrease in pin access points for connection to power and signal wiring, particularly as the industry moves towards smaller technology nodes like 7-nm and beyond.
Innovation Solution
The implementation of semiconductor integrated circuit devices with ultra-short standard cell heights, specifically using three-track or n-track cell heights where n is four or less, which allows for sufficient pin access through innovative interconnect structures on both sides of the standard cells, enabling efficient signal and power track connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If standard cell height is reduced to enable scaling, then device integration density is improved, but pin access points decrease leading to poor routeability
Solution Approach 1:
The patent introduces a third dimension by forming interconnect structures that extend through the thickness of the substrate, enabling vertical routing paths. Through-holes penetrating the substrate allow pin access points to reach external connections without increasing the horizontal footprint of the standard cell, thus maintaining small cell area while improving routeability.
Solution Approach 2:
The patent segments the routing function by separating horizontal interconnects (within the standard cell plane) from vertical interconnects (through-holes penetrating the substrate). This segmentation allows the standard cell to maintain its compact dimensions while routing signals through multiple spatial layers, resolving the conflict between small area and good routeability.
2Area of moving object
If standard cell height is reduced, then circuit area is reduced, but the number of pin access points decreases
Solution Approach 1:
By utilizing the vertical dimension through substrate-penetrating through-holes, the patent enables multiple pin access points to be achieved without increasing the horizontal area of the standard cell. The through-holes provide additional routing paths that access pins from the opposite side of the substrate, effectively increasing pin availability within the same footprint.
Solution Approach 2:
The patent implements nested routing where through-holes are positioned within or adjacent to the standard cell structure, allowing pin access points to be integrated into the compact cell design. The through-holes are strategically placed to provide access to internal pins without requiring additional horizontal space, nesting the vertical routing infrastructure within the cell's spatial envelope.
Data Source
AI summary
Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.