Ultra-short Gate Formation Using Dielectric Spacer Etching
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Solution Overview
Problem
Conventional photolithography techniques are limited in achieving gate widths smaller than 0.35 to 0.40 microns, requiring expensive advanced lithography methods for further miniaturization in semiconductor devices.
Innovation Solution
A method involving the formation of a first gate pattern with a recess, followed by depositing a dielectric spacer to create a second recess with a narrower width, using a combination of photolithography and spacer etch processes, including dry etch techniques like reactive ion etch and inductively coupled plasma, to achieve gate widths less than 0.25 microns without the need for advanced lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to define gates, then the manufacturing process is simple and cost-effective, but the gate width cannot be reduced below 0.35 to 0.40 microns
Solution Approach 1:
The gate formation process is segmented into multiple stages: first forming a preliminary gate pattern at relaxed dimensions (0.35-0.40 microns) using conventional photolithography, then using dielectric spacers to define the final ultra-short gate dimensions (0.05-0.25 microns). This segmentation allows each stage to operate at optimal dimensions, avoiding the need for advanced lithography while achieving sub-0.25 micron gates.
Solution Approach 2:
The invention transitions from two-dimensional photolithographic patterning to three-dimensional spacer-based patterning. By depositing conformal dielectric layers on the sidewalls of the preliminary gate structure, the final gate width is defined by the spacer thickness rather than direct lithographic exposure, effectively moving the critical dimension control to a different dimensional regime where conventional lithography limitations no longer apply.
2Manufacturing precision
If advanced lithography methods are used to achieve smaller gate widths, then gate miniaturization is achieved, but capital equipment costs and fabrication costs increase significantly
Solution Approach 1:
The preliminary gate pattern serves as a template or copy that defines the location and basic dimensions of the final gate. The critical dimension information is then copied from the spacer thickness (deposited at controlled thickness) rather than directly from the lithographic pattern, allowing ultra-precise dimension control using standard deposition equipment rather than expensive advanced lithography tools.
Solution Approach 2:
The invention changes the controlling parameter for gate width from lithographic exposure parameters (wavelength, numerical aperture) to deposition parameters (spacer layer thickness, conformal coverage). This parameter change allows the use of standard PECVD or ALD equipment to achieve sub-0.25 micron dimensions that would otherwise require costly extreme UV or electron beam lithography.
3Manufacturing precision
If dielectric spacers are deposited to define narrower recesses, then gate width is reduced below photolithography limits, but the process complexity increases
Solution Approach 1:
The dielectric spacer layer serves multiple functions simultaneously: it defines the final gate width through its thickness, provides sidewall protection during subsequent etching, and establishes the precise location of the ultra-short gate. This multi-functionality consolidates what would otherwise require separate process steps into a single deposition operation, making the increased precision achievable without proportionally increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with gate widths in the range of 0.05 to 0.25 microns, overcoming the limitations of conventional photolithography while reducing the need for costly advanced lithography equipment.
Implementation Method 1
depositing a dielectric spacer layer on the semiconductor including the first gate pattern, the dielectric spacer layer being formed on a top surface of the semiconductor and on surfaces of the first recess
Implementation Method 2
performing a dry etch process to remove the dielectric spacer layer from the top surface of the semiconductor and from a portion of the first recess
Implementation Method 3
the dry etch process includes a reactive ion etch and/or inductively coupled plasma
Implementation Method 4
depositing a carbon based polymer on a side wall of the dielectric spacer by using a fluorine carbon gas having a carbon to fluorine ratio that is equal to or greater than about 1:2
Data Source
AI summary
Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width. A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.