Ultra-Thick Copper Deposition via Segmented Electroplating
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Solution Overview
Problem
Traditional semiconductor processing techniques struggle to scale for ultra-thick metal layers, leading to wafer warpage issues and limitations in achieving desired thickness for reducing series resistance in RF ICs, as conventional Damascene processes are inadequate for depositing copper layers thicker than 3 μm without significant warpage.
Innovation Solution
A new method and structure for depositing ultra-thick copper layers using a trapezoidal shape with a more acute angle, allowing for thicker UTM copper deposition without wafer warpage, involving a combination of patterning, electroplating, and chemical-mechanical planarization, and using a barrier and seed layer with better conformity and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional Damascene processes are used to deposit copper layers, then manufacturing process is simple, but copper layer thickness is limited to less than 3 μm due to wafer warpage
Solution Approach 1:
The patent segments the copper deposition process into multiple stages: first forming a seed layer, then depositing a first copper layer, followed by a second copper layer, and finally a third copper layer. This segmentation allows each layer to be deposited and planarized separately, preventing excessive stress accumulation that causes warpage while achieving ultra-thick overall copper thickness exceeding 3 μm
Solution Approach 2:
The patent applies preliminary chemical-mechanical planarization (CMP) to create a flat surface before depositing each subsequent copper layer. This preliminary action ensures uniform deposition and stress distribution, preventing warpage while enabling thicker copper layers to be formed without compromising manufacturing precision
2Reliability
If thicker copper layers are deposited to reduce series resistance, then electrical performance improves, but wafer warpage increases significantly
Solution Approach 1:
The patent divides the thick copper deposition into multiple thinner sub-layers (first, second, and third copper layers), each deposited and planarized separately. This segmentation reduces the stress accumulation in each individual layer while achieving the desired total thickness, thereby reducing series resistance without causing significant wafer warpage
Solution Approach 2:
The patent employs periodic cycles of copper deposition followed by chemical-mechanical planarization. Each cycle deposits a portion of the required copper thickness and then planarizes the surface, creating a periodic pattern of deposition and flattening that maintains wafer flatness throughout the process while accumulating the necessary copper thickness for low series resistance
3Manufacturing precision
If multiple copper layers are deposited with planarization between each, then ultra-thick copper without warpage is achieved, but process complexity increases
Solution Approach 1:
The patent merges the deposition and planarization operations into an integrated process flow where each copper layer is deposited and immediately planarized in sequence. This merging approach, while adding steps, ensures uniform thickness control and stress management, achieving ultra-thick copper layers without warpage through systematic combination of deposition and planarization operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the achievement of UTM thicknesses greater than 3 μm, such as 6 μm or 10 μm, without significant wafer warpage, effectively reducing series resistance in inductive loops and other applications, while maintaining structural integrity.
Implementation Method 1
selectively plating conductive materials in the plurality of trenches
Data Source
AI summary
The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.