Ultra Thin FET With Copper Electrodes
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Solution Overview
Problem
MOSFET devices with thick substrates have high on-resistance due to substrate resistance, making them mechanically fragile and difficult to handle during fabrication and packaging, despite thinning to 60 microns for reduced resistance.
Innovation Solution
Thinning wafers to a thickness of 3 microns or less, with massive copper electrodes on both surfaces for mechanical rigidity, and using a novel process involving wafer carrier mounts and electroless backside contacts to enhance handling and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wafer is thinned to reduce substrate resistance, then on-resistance decreases, but mechanical strength deteriorates making the device fragile and difficult to handle
Solution Approach 1:
The patent applies this principle by using a thin silicon foil (1-10 microns thick) instead of a thick substrate, achieving low on-resistance while the foil itself would be mechanically weak without support structures
Solution Approach 2:
The patent combines thin silicon foil with thick copper electrodes (20 microns thick) on both surfaces to create a composite structure that achieves both low electrical resistance and mechanical strength through the combination of different materials with complementary properties
2Reliability
If the wafer is thinned to 60 microns to reduce resistance, then on-resistance decreases, but handling difficulty increases during fabrication and packaging
Solution Approach 1:
The patent uses an even thinner silicon foil (1-10 microns) compared to conventional 60 micron wafers, achieving lower resistance while using copper electrodes to enable handling
Solution Approach 2:
The thick copper electrodes serve as intermediary elements that provide mechanical support and handling capability for the thin silicon foil, making the device easy to handle during fabrication and packaging while maintaining low on-resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach significantly reduces on-resistance while providing sufficient mechanical strength for easy handling and packaging, allowing for more efficient fabrication and packaging of MOSFET devices.
Implementation Method 1
The top surface of the foil has a relatively massive copper electrodes (20 microns thick, for example), and the bottom of the wafer may also have a similar massive (20 microns, for example) bottom electrodes to lend mechanical rigidity to the silicon foil.
Implementation Method 2
A novel process for producing this result is also disclosed involving wafer carrier mounts and electroless backside contacts to enhance handling and electrical connectivity.
Data Source
AI summary
Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.