Ultra-Thin Fin Transistors via III-V Subfin Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in optimizing the performance of germanium-based devices and multi-gate transistors, particularly in reducing channel resistance and integrating non-Si channel materials like SiGe and III-V materials on Si wafers, while also struggling to achieve ultra-thin fin profiles for improved electrostatics and defect-free semiconductor material growth.
Innovation Solution
The development of field effect transistors with ultra-thin fin profiles involves forming a subfin portion from III-V semiconductor materials like GaAs within an aspect ratio trapping trench, followed by growing an active fin portion from group IV semiconductors like germanium on a pristine surface, and then thinning and etching to create a high-quality, defect-free active fin structure, which allows for improved electrostatics and reduced channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form fins, then manufacturing process is simpler, but fin profile cannot achieve ultra-thin dimensions and electrostatics are degraded
Solution Approach 1:
The fin structure is segmented into two distinct portions: a subfin portion formed from III-V semiconductor material and an active fin portion formed from group IV semiconductor material. This segmentation allows each portion to be optimized independently - the subfin provides mechanical support and defect-free growth substrate, while the active fin achieves ultra-thin profile for superior electrostatics and channel control.
Solution Approach 2:
The subfin portion acts as an intermediary substrate that enables the formation of ultra-thin active fin portions. By providing a lattice-matched, defect-free III-V semiconductor foundation, the subfin mediates the growth of group IV semiconductor material to achieve thicknesses below conventional lithographic limits while maintaining structural integrity.
2Reliability
If germanium-based materials are used for high hole mobility, then drive current performance is improved, but channel resistance and defects increase
Solution Approach 1:
Different regions of the fin structure have different material compositions optimized for their specific functions. The subfin portion uses III-V semiconductor material providing lattice-matched, defect-free growth, while the active fin portion uses group IV semiconductor material (germanium or SiGe) providing high hole mobility. This local quality differentiation resolves the contradiction between achieving high performance and minimizing defects.
Solution Approach 2:
The fin structure employs a composite material system combining III-V semiconductor subfin material with group IV semiconductor active fin material. This composite structure leverages the defect-free growth characteristics of III-V materials and the high carrier mobility of group IV materials, achieving both reliability and performance simultaneously.
3Reliability
If non-Si channel materials like SiGe and III-V materials are integrated on Si wafers, then device performance is enhanced, but process integration difficulty increases
Solution Approach 1:
The invention changes the material parameter (crystal structure and composition) of the fin substrate from conventional silicon to III-V semiconductor material. This parameter change enables lattice-matched growth of group IV semiconductor channels, resolving integration challenges while achieving superior device performance through optimized material properties.
4Manufacturing precision
If fin thickness is reduced for improved electrostatics, then channel control is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The subfin portion serves as a temporary, sacrificial structure that enables the creation of ultra-thin active fins. This disposable substrate provides the necessary mechanical support during fabrication and growth processes, allowing achievement of thicknesses that would otherwise be impossible to manufacture, after which the structure is optimized for final device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of transistors with ultrathin active fin profiles that offer improved electrostatics and reduced defects, enhancing the performance of germanium-based devices and multi-gate transistors by leveraging the high hole mobility of germanium and the defect-free growth of III-V materials, thereby addressing the limitations of existing technologies.
Implementation Method 1
A III-V semiconductor material is formed in the trench and above a top surface of the insulation layer. A group IV semiconductor material is formed on the III-V semiconductor material in the trench and extending above the top surface of the insulation layer
Data Source
AI summary
A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.