Ultra-thin Redistribution Structure for Semiconductor Package Height Reduction

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Solution Overview

Problem

The challenge in semiconductor packaging is to miniaturize multi-chip packages while maintaining process simplicity, particularly in reducing the package height to meet demands for smaller, lighter, and more functional electronic devices.

Innovation Solution

A semiconductor package with an ultra-thin redistribution structure, including a semiconductor die and insulating encapsulants, is developed, where the ultra-thin redistribution structure is formed and tested for electrical continuity before die bonding, and the package is encapsulated with multiple insulating layers to reduce height and enhance stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If conventional redistribution structures are used, then the package height is larger, but the miniaturization requirement cannot be met

Engineering Contradiction:
Improvepackage heightVSAvoidredistribution structure thickness control
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by transitioning from conventional thick redistribution structures to ultra-thin redistribution structures with controlled thickness. This is achieved through modified fabrication processes that enable precise control of the redistribution layer thickness, allowing significant reduction in package height while maintaining electrical functionality and structural integrity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If circuit test is performed after die bonding, then the process sequence is simpler, but die loss occurs due to undetected defects

Engineering Contradiction:
ImproveyieldVSAvoidprocess sequence
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by performing circuit testing on the ultra-thin redistribution structure before die bonding occurs. This early testing stage allows defects to be detected and addressed prior to committing the die to the package, preventing costly die loss while maintaining a streamlined process sequence through integrated test points and accessible testing methodology.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10522512B2Semiconductor package and manufacturing method thereof
Publication Date: 2019.12.31 POWERTECH TECHNOLOGY INC
  • US10522512B2 patent drawing
  • US10522512B2 patent drawing
  • US10522512B2 patent drawing

AI summary

A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.