Ultra-Thin Silicon HDI Packaging for Fine-Pitch Chip Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing cost of advanced semiconductor packaging due to the need for larger silicon interposers to achieve high-density chip interconnections, which is exacerbated by the use of expensive through-silicon-vias and rising material costs as interconnection pitch is reduced.
Innovation Solution
A high-density-interconnection packaging structure using ultra-thin silicon as an intermediate connector with fine interconnections of 10 μm or less, combined with ordinary vias instead of through-silicon-vias, and a dual-pitch metal array system to connect chips and an organic substrate, reducing packaging costs and manufacturing expenses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If larger silicon interposers are used to achieve high-density chip interconnections, then interconnection density is improved, but packaging cost and material cost increase significantly
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D vertical interconnection by forming through-silicon-vias (TSVs) that penetrate the silicon interposer thickness direction. This enables chips to be stacked vertically with interconnection pitches of 10 μm or less, achieving high-density interconnection without increasing the lateral footprint of the silicon interposer.
Solution Approach 2:
The patent changes the interconnection architecture from surface-level routing to subsurface vertical routing through TSVs. By modifying the interconnection dimension from 2D to 3D and reducing the via diameter to 10 μm or less, the patent achieves fine-pitch interconnection with reduced material usage and cost.
2Manufacturing precision
If through-silicon-vias are used to achieve fine-pitch interconnections, then interconnection precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent optimizes the TSV parameters by controlling the via diameter to be 10 μm or less and adjusting the metal filling composition (copper, aluminum, or tungsten). This parameter optimization achieves fine-pitch interconnection while reducing the complexity and cost of the manufacturing process compared to conventional larger-via approaches.
3Manufacturing precision
If interconnection pitch is reduced to achieve high-density packaging, then chip interconnection density is improved, but material cost increases
Solution Approach 1:
The patent reduces the via diameter parameter to 10 μm or less and optimizes the metal filling composition, thereby achieving fine-pitch interconnection with reduced material consumption. This parameter change enables high-density packaging while controlling material costs.
Solution Approach 2:
The patent employs composite material structures by combining the silicon interposer with metal fillings (copper, aluminum, or tungsten) in the TSVs. This composite approach enables fine-pitch interconnection with optimized material usage, reducing overall material cost while maintaining interconnection density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance and high-bandwidth 2.5D/3D IC packaging with reduced packaging costs by using ultra-thin silicon connectors and ordinary vias, achieving fine interconnections while minimizing material usage and manufacturing costs.
Implementation Method 1
bonding the silicon connector across the chips by arranging to connect the third metal array and the first metal array
Implementation Method 2
forming a molding layer, covering the chips and the silicon connector
Implementation Method 3
grinding the molding layer to expose the silicon connector first, then continuing to grind the silicon connector until the silicon connector becomes ultra-thin silicon
Implementation Method 4
filling the vias with metal materials, wherein the metal materials are connected to the second metal array
Implementation Method 5
forming metal pillar structures over the metal-filled vias, wherein the metal pillar structures are connected to the metal materials in the vias, and wherein the metal pillar structures are also connected to an organic substrate
Data Source
AI summary
A high-density-interconnection (HDI) packaging structure and a method for preparing the same are provided. The method comprises: disposing a first metal array with a first pitch and a second metal array with a second pitch on chips; disposing a third metal array on a silicon connector, and bonding the silicon connector to cross the chips; forming a molding layer to cover the chips and the silicon connector; grinding the molding layer and the silicon connector to form ultra-thin silicon; forming vias in the molding layer, with the vias aligned to the second metal array; filling the vias with metal materials, wherein the metal materials are connected to the second metal array; forming metal pillars and connecting the metal pillars to an organic substrate. The present disclosure uses ultra-thin silicon as an intermediate connector to achieve fine interconnection between HDI chips at a pitch of 10 um or less.