Ultra-Thin Wafer Stacking with Stop Layers for 3D Chip Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high integration and high speed due to limitations in miniaturization and stacking efficiency, particularly in semiconductor planar packaging.
Innovation Solution
A method for manufacturing a semiconductor stack structure with ultra-thin dies involves forming a stop layer structure in semiconductor substrates, flipping and bonding wafers, and performing backside grinding and thinning processes to create ultra-thin wafers, allowing for multiple layers to be stacked with improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar packaging technology is used, then manufacturing simplicity is maintained, but integration density and operating speed are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) packaging to three-dimensional (3D) stacking architecture. Multiple semiconductor wafers are bonded together in vertical layers, with through-silicon vias providing electrical interconnections between layers. This dimensional transition enables significantly higher integration density by utilizing the vertical space above the substrate, allowing numerous devices to be stacked in a compact footprint.
2Productivity
If wafer thickness is reduced to increase stacking layers, then integration density improves, but mechanical strength and handling difficulty deteriorate
Solution Approach 1:
The patent applies local reinforcement strategies to ultra-thin wafers. Reinforcement structures such as support frames or carrier substrates are introduced at specific locations where mechanical strength is critical during handling and processing. This allows the wafer body to remain ultra-thin for high stacking density while localized reinforcement provides the necessary mechanical robustness for manufacturing and assembly.
Solution Approach 2:
The patent introduces intermediary support structures between ultra-thin wafers during the stacking process. These intermediaries, such as temporary carriers or support substrates, provide mechanical strength to fragile thin wafers during handling and bonding operations. After bonding, the intermediaries are removed, leaving the ultra-thin wafers securely stacked. This mediator approach enables processing of wafers that would otherwise be too fragile to handle.
3Productivity
If multiple bonding and thinning processes are performed to create ultra-thin stacked wafers, then integration density and electrical performance improve, but manufacturing complexity and process time increase
Solution Approach 1:
The patent performs preliminary wafer thinning and through-silicon via formation on individual wafers before stacking. By preparing each wafer in advance with the required thickness and interconnection structures, the actual stacking process becomes simpler and faster. This preliminary preparation includes bonding wafers to support substrates, forming vias, and thinning to target dimensions before the final assembly, thereby reducing the complexity of the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables high integration and high speed performance by allowing up to 57 layers of ultra-thin semiconductor chips to be stacked, with each layer thinner than 12 microns, enhancing electrical efficiency and characteristics.
Implementation Method 1
the silicon nitride layer is manufactured by carrying out a nitrogen ion implantation process at a first depth of the semiconductor substrate first and then carrying out a high temperature treatment process to form the silicon nitride layer in a nitrogen ion implanted region
Implementation Method 2
carrying out a high temperature treatment process to form the silicon nitride layer in a nitrogen ion implanted region
Implementation Method 3
carrying out a first backside grinding process from the backside of the second semiconductor wafer to remove a portion of the second substrate part of the second semiconductor wafer
Implementation Method 4
enabling the inner connection layer of the first semiconductor wafer and the inner connection layer of the second semiconductor wafer to be opposite to each other and bonded together by hybrid bonding
Data Source
AI summary
A method includes manufacturing a plurality of wafers each having a substrate having an active surface and a backside, and a stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside; on a first wafer of the plurality of wafers, removing the second substrate part and the stop layer; bonding a second wafer of the plurality of wafers on the first wafer with first substrate part of the second wafer facing a surface of the first wafer that is exposed by removing the stop layer and, on the second wafer, performing the same processes of removing the second substrate part and stop layer of the second wafer; repeating the bonding and removing the second substrate part and stop layer with one or more wafers to form a stack of wafers.