Ultrasonic IC Testing Pads for Inaccessible I/O Inspection

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Solution Overview

Problem

Current methods for testing integrated circuits (ICs) are inefficient, especially when chips are attached upside down or have inaccessible I/O ports, and the non-recurring engineering costs for developing new chips with different configurations are prohibitively high, particularly in military/defense applications where low device counts and long development times hinder the use of high-performance systems.

Innovation Solution

The development of sonically enabled PADS (SEPADS) and SETestPOINTS using aluminum nitride transducers for ultrasonic communications, allowing for testing and alignment without electrical connections, along with micro-manipulation and alignment using bulk-PZT lateral bimorph technology and ultrasonically active alignment marks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If traditional electrical connection methods are used for testing ICs, then electrical signals can be transmitted for testing, but the I/O ports become inaccessible when chips are attached upside down, making testing impossible

Engineering Contradiction:

Improvetesting accessibilityVSAvoidchip orientation flexibility

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent replaces electrical connection-based testing with acoustic wave-based testing. Acoustic waves can penetrate through the chip substrate and interact with internal structures without requiring access to I/O ports, enabling testing of upside-down mounted chips. The acoustic transducer converts electrical signals to acoustic waves that propagate through the chip and reflect off internal features, providing testing capability independent of chip orientation.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If new chips with different configurations are developed to meet performance requirements, then system performance improves, but non-recurring engineering costs and development time increase significantly

Engineering Contradiction:

Improvesystem performanceVSAvoiddevelopment time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements acoustic testing during the wafer fabrication stage before chips are diced and packaged. This preliminary testing identifies functional chips and defects early in the manufacturing process, allowing only good chips to proceed to assembly. By performing testing before final chip configuration is determined, the system can adapt chip usage to meet performance requirements without requiring expensive re-engineering of new chip designs.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If comprehensive testing is performed on all chips, then defect detection accuracy improves, but testing time and cost increase

Engineering Contradiction:

Improvedefect detection accuracyVSAvoidtesting throughput

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the chip testing process into multiple acoustic measurement stages, each targeting specific defect types or chip regions. Different acoustic transducer frequencies and wave modes are used to detect different defect categories. This segmented approach allows comprehensive defect detection while maintaining throughput by processing multiple chips in parallel and prioritizing critical defect detection.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent varies acoustic wave parameters such as frequency, amplitude, and pulse duration to optimize detection of different defect types. By changing acoustic parameters rather than performing multiple separate tests, the system achieves comprehensive defect detection with improved throughput. Different frequency ranges are used to detect different sizes and types of defects within the same testing sequence.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient testing and alignment of ICs without electrical connections, reduces non-recurring engineering costs, and accelerates the development and deployment of high-performance systems by allowing for non-contact testing and bonding of small chiplets with high precision.

Implementation Method 1

aluminum nitride transducers configured to sonically interrogate the circuit layer

Methodology Applied

Scientific EffectPiezoelectric effect: Piezoelectric Effect

Implementation Method 2

ultrasonic transducers configured to sonically interrogate the circuit layer

Methodology Applied

Scientific EffectUltrasonic vibration: Ultrasonic Vibration

Implementation Method 3

micro-manipulation and alignment using bulk-PZT lateral bimorph technology

Methodology Applied

Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS11867754B2Sonic testing method, apparatus and applications

Publication Date: 2024.01.09 CORNELL UNIVERSITY

AI summary

A system, comprising: (i) an interposer layer; (ii) a circuit layer positioned on the interposer layer and comprising a plurality of sonically-enabled pads; and (iii) an interrogator layer positioned on the circuit layer and comprising a plurality of ultrasonic transducers configured to sonically interrogate the circuit layer; wherein the sonically-enabled pads are configured to generate an electrical signal in response to sonic interrogation from the interrogator layer, if the sonically-enabled pad is functional.