Ultrasonic Pixel Receiver Layout for Parasitic Capacitance Cancellation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ultrasonic imaging apparatuses using thin-film transistor (TFT) technology suffer from low voltage conversion efficiency and high noise, which are not adequately addressed by existing technologies.
Innovation Solution
A pixel receiver with a first metallization layer above a substrate and a second metallization layer between the first layer and the substrate, where a second voltage is applied to reduce parasitic capacitance, enhancing sensitivity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin-film transistor (TFT) technology is used for pixel receiver circuits, then the device can be manufactured with existing semiconductor processes, but voltage conversion efficiency is low and noise is high
Solution Approach 1:
The patent changes the technological parameter from TFT to CMOS technology for the pixel receiver circuits. This parameter change resolves the contradiction by achieving both high voltage conversion efficiency and low noise (improved reliability) while maintaining compatibility with existing semiconductor manufacturing processes (ease of manufacture).
2Ease of manufacture
If thin-film transistor (TFT) technology is used for pixel receiver circuits, then the device can be manufactured with existing semiconductor processes, but noise is high
Solution Approach 1:
The patent changes the technological parameter from TFT to CMOS technology for the pixel receiver circuits. This parameter change resolves the contradiction by achieving low noise (reduced harmful factors) while maintaining compatibility with existing semiconductor manufacturing processes (ease of manufacture).
3Measurement precision
If a large metallization layer is used above the substrate, then the sensitivity to ultrasonic waves is improved, but parasitic capacitance increases
Solution Approach 1:
The patent introduces an intermediate metallization layer between the first metallization layer (for sensitivity) and the substrate. This intermediary layer, when biased with an appropriate voltage, reduces the parasitic capacitance between the first metallization layer and the substrate, thereby resolving the contradiction between sensitivity and parasitic capacitance.
4Measurement precision
If a large metallization layer is used above the substrate, then the sensitivity to ultrasonic waves is improved, but voltage conversion efficiency decreases
Solution Approach 1:
The patent introduces an intermediate metallization layer between the first metallization layer (for sensitivity) and the substrate. This intermediary layer, when biased with an appropriate voltage, reduces the parasitic capacitance between the first metallization layer and the substrate, thereby resolving the contradiction between sensitivity and voltage conversion efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the sensitivity and efficiency of ultrasonic imaging by effectively reducing parasitic capacitance, leading to better voltage conversion and noise reduction.
Implementation Method 1
The receiving piezoelectric layer converts the reflected wave into voltages at respective inputs of the pixel sensors of the pixel receiver
Implementation Method 2
a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.