Ultrasound Receiving Module With Shift Register Delay Compensation
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Solution Overview
Problem
Commercial ultrasound imaging devices face compatibility and expandability issues due to varying numbers of channels, requiring additional post-stage processing units for signal rendering, and existing beam formers struggle with efficient delay and sum operations across channels with different path lengths.
Innovation Solution
The proposed ultrasound receiving module and system utilize N sets of shift register arrays, a delay controller, FIFO buffers, a time multiplexer, a multiplier, and an accumulator to process return-wave signals from multiple channels, performing interpolation and delay compensation to generate image values, allowing for efficient processing and expansion without altering hardware architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different numbers of channels are used in commercial ultrasound imaging devices, then compatibility and expandability issues arise, but adding post-stage processing units for each channel increases device complexity
Solution Approach 1:
The patent implements a universal beam former architecture that can handle different channel configurations (e.g., 16, 32, 64 channels) through a single standardized processing unit. The shift register arrays and delay controllers are designed to accommodate variable channel numbers without requiring additional post-stage processing units, achieving multi-functionality across different device specifications.
Solution Approach 2:
The beam former is divided into modular components: N sets of shift register arrays (each with M registers), N delay controllers, and shared post-stage units (multiplier and accumulator). This segmentation allows each module to be independently configured for different channel counts while sharing common resources, reducing overall device complexity.
2Measurement precision
If delay compensation is performed on channels with different path lengths, then signal constructive interference is maximized, but processing time and computational resources increase
Solution Approach 1:
The patent pre-calculates and stores delay values in delay tables for all possible channel combinations before actual signal processing. During operation, the delay controller simply retrieves pre-computed delay values and applies them through shift registers, avoiding real-time complex calculations and significantly reducing processing time while maintaining precise signal alignment.
Solution Approach 2:
The system uses periodic clock signals to control the shift registers, which sequentially shift signal samples through fixed stages. This periodic operation replaces continuous variable delay adjustments with discrete time-step shifts, simplifying the timing control and reducing processing overhead while achieving sufficient delay compensation accuracy.
3Measurement precision
If interpolation operations are performed on shift register data, then delay precision is improved, but computational complexity increases
Solution Approach 1:
The patent changes the representation of delay values from continuous analog delays to discrete digital shift amounts. By using integer-based shift register positions instead of floating-point delay times, the system achieves sufficient precision through parameter quantization, avoiding complex interpolation calculations while maintaining adequate delay accuracy for ultrasound beamforming.
Data Source
AI summary
An ultrasound receiving method is provided. N return-wave signals corresponding to N channels are respectively stored in N set of shift register arrays. Each set includes a delay filter unit and M shift registers. A delay controller is utilized to assign a set of coefficients to the delay filter unit to perform an interpolation operation on data of the M shift registers to obtain an output value. The delay controller is utilized to decide delay time of each channel according to a delay table, and accordingly to control a time multiplexer to switch and output the N output values in order. A multiplier is utilized to multiply the output value received from the time multiplexer by a weighted value corresponding to the channel to obtain a corrected value. An accumulator is utilized to accumulate the N corrected values to obtain an image value.