Hardware Data Transfer Unit for UMTS Protocol Stack Optimization
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Solution Overview
Problem
Conventional UMTS mobile equipment protocol stacks face inefficiencies due to high MIPS consumption in data movements and buffer management, particularly in handling variable-length MAC-hs PDUs, which leads to performance and energy inefficiencies and increased silicon costs.
Innovation Solution
A smart partitioning of hardware and software components, where a hardware data mover performs data copy and transfer operations under software control, allowing for efficient data processing and reduced memory and bus accesses, with a software control unit managing memory allocation and buffer management to optimize data movement and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SW-based solutions are used to process each sub-layer and copy packet data to separate buffers, then flexibility and ease of upgrading are improved, but MIPS consumption increases and performance decreases
Solution Approach 1:
The patent divides the protocol stack processing into distinct hardware modules (MAC-hs processing module, RLC processing module, ciphering module) that can operate independently and in parallel. Each module handles specific sub-layer functions, enabling simultaneous processing of multiple protocol layers without requiring sequential software execution, thus improving performance while maintaining flexibility through modular design.
Solution Approach 2:
The patent introduces a shared memory structure that acts as an intermediary between hardware processing modules and software control. This shared memory allows hardware modules to access packet data directly without software intervention for data copying, eliminating bottlenecks while software retains control over processing logic and buffer management strategies.
2Quantity of substance
If maximum memory size is used to buffer variable-length MAC-hs PDUs, then data buffering capability is improved, but silicon cost increases
Solution Approach 1:
The patent implements dynamic buffer allocation where the memory space for MAC-hs PDUs is allocated based on the actual size requirements of incoming packets rather than reserving maximum memory capacity. The buffer size adapts to the variable length of MAC-hs PDUs, allowing efficient use of memory resources without over-provisioning, thus reducing silicon cost while maintaining adequate buffering capacity.
3Productivity
If data is moved between multiple buffers for MAC and RLC processing, then processing capability is improved, but energy consumption and performance are affected negatively
Solution Approach 1:
The patent merges the buffer spaces for MAC-hs and RLC processing into a shared memory structure. Instead of moving data between separate MAC buffers and RLC buffers, both processing modules access the same memory region, eliminating redundant data copies and reducing energy consumption while maintaining the ability to process both protocol layers efficiently.
4Speed
If HW acceleration is implemented for data movement and encryption, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent designs hardware processing modules that can perform multiple functions: MAC-hs processing, RLC processing, and ciphering operations. By making these hardware modules multi-functional, the system achieves high processing speed for various protocol operations without requiring separate dedicated hardware for each function, thus limiting the increase in device complexity while maintaining high performance.
Data Source
AI summary
A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.