UMTS Downlink Interleaver Memory Reduction via DTX Relocation
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Solution Overview
Problem
The existing 3GPP standard for downlink transmissions in UMTS requires inefficient memory usage due to the need to store four-valued symbols, which doubles the memory size required for data storage in the first interleaver, and involves complex processing for DTX and p-bit insertion and removal.
Innovation Solution
The method involves writing data from multiple channels as one-bit symbols to memory, performing interleaving, and inserting DTX bits only on the output side of the first interleaver, eliminating the need for storing four-valued symbols and reducing hardware requirements by combining DTX insertion points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If four-valued symbols are stored in the first interleaver memory to support DTX insertion, then DTX handling capability is improved, but memory size doubles and hardware complexity increases
Solution Approach 1:
The patent extracts the DTX insertion operation from the first interleaver and relocates it to the second interleaver. This removes the need for the first interleaver to store four-valued symbols, reducing its memory requirements back to one-bit symbols while maintaining DTX handling capability through the second interleaver's insertion process.
Solution Approach 2:
The patent inverts the conventional approach by performing DTX insertion at the second interleaver instead of the first interleaver. This reversal of the operation sequence allows the first interleaver to use simpler one-bit symbol storage while achieving the same functional outcome through the second interleaver's processing.
2Adaptability or versatility
If DTX insertion is performed at both first and second interleavers for flexible position multiplexing, then multiplexing flexibility is improved, but hardware complexity and processing overhead increase
Solution Approach 1:
The patent merges the DTX insertion function into a single location at the second interleaver, eliminating the need for separate DTX insertion hardware at the first interleaver. This consolidation maintains flexible position multiplexing capability while reducing overall hardware complexity and processing overhead.
3Adaptability or versatility
If p-bit insertion and removal operations are implemented according to standard, then measurement gap support is improved, but processing complexity increases
Solution Approach 1:
The patent performs p-bit insertion at the second interleaver as a preliminary action before final transmission, and removes them as a final action after reception. This timing of operations supports measurement gap functionality while simplifying the overall processing complexity compared to intermediate insertion and removal operations.
Data Source
AI summary
In a communication method, data from a plurality of channels is combined into a composite channel by writing data from the plurality of channels as one-bit symbols to a memory, and reading out the data from memory to form the composite channel. The combining of radio frames from the channels forms a coded composite transport channel for transmitting the data in the downlink. To form the coded composite transport channel, an input process is initiated to write data for each radio frame of a transport channel as one bit symbols to a memory of an interleaver. On an output side of the interleaver, an output process to read out the data stored in the memory is performed to form the coded composite transport channel.