Angled Wafer Transistors for Dense Memory Cell Layouts
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Solution Overview
Problem
Conventional memory devices face limitations in transistor density due to the alignment constraints of semiconductor transistors with control lines, leading to compromised performance and reduced memory scaling capabilities.
Innovation Solution
The use of angled transistors formed through a pair of unaligned wafers, where the semiconductor structure's crystal direction is not parallel or perpendicular to the substrate's crystal direction, allowing for increased transistor density without lattice mismatch issues, enabling higher memory cell density and flexible orientations for MOSFETs and TFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are aligned with control lines in conventional memory cells, then the manufacturing process is simpler, but the memory cell density is limited
Solution Approach 1:
The patent applies asymmetry by forming transistors at angled orientations (e.g., 45 degrees) relative to the control lines rather than aligning them parallel or perpendicular. This asymmetric arrangement allows more transistors to be packed into the same area, increasing memory cell density while maintaining manufacturability through standard photolithography processes.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar transistor alignment to angled three-dimensional positioning. By forming transistors at oblique angles relative to the substrate plane and control lines, the invention effectively utilizes additional spatial dimensions to increase packing density without requiring further scaling of critical dimensions.
2Quantity of substance
If critical dimensions are scaled down to increase density, then memory cell density improves, but the manufacturing process becomes more complex and costly
Solution Approach 1:
Instead of scaling down critical dimensions (width, length), the patent changes the orientation parameter of transistor formation. By forming transistors at angled orientations rather than reducing their dimensions, the invention achieves increased density while maintaining the same manufacturing process parameters, avoiding the complexity and cost associated with advanced scaling.
3Quantity of substance
If angled transistors are formed with misaligned crystal structures, then transistor density increases, but lattice mismatch issues arise compromising performance
Solution Approach 1:
The patent introduces an intermediary substrate with a specific crystal orientation that serves as a bridge between the original substrate and the angled transistor structures. This intermediary layer allows formation of transistors at angled orientations while maintaining proper crystal structure alignment, thereby achieving increased density without lattice mismatch issues.
Solution Approach 2:
The patent segments the transistor formation process into separate stages: first forming the substrate with its crystal structure, then forming angled mandrels and transistors independently. This segmentation allows the crystal structure and transistor orientation to be optimized separately, enabling angled transistors to be formed without compromising crystal alignment.
Data Source
AI summary
IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.