Unary-Coded MAC Circuit Using Vector Quantized Multiplexing
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Solution Overview
Problem
Stochastic computing systems typically require a multiply-accumulate (MAC) operation, which are the challenges of integrating and optimizing the stochastic to consecutive edge modulation (CEM) converter comprising:[0034] a first aspect, the invention provides circuitry for performing a convolutional Neural Network (CNN) circuitry comprising:[0032] a third aspect, the invention provides stochastic to consecutive edge modulation (CEM) converter comprising:[0033] a first aspect, the invention provides circuitry for performing a convolutional Neural Network (CNN) circuitry comprising:[0034] a second aspect, the invention provides circuitry for integrating and optimizing the stochastic to consecutive edge modulation (CEM) converter comprising:[0035] a first aspect, the invention provides circuitry for performing a convolutional Neural Network (CNN) circuitry comprising:[0034] a second aspect, the invention provides circuitry for integrating and optimizing the stochastic to consecutive edge modulation (CEM) converter comprising:[0035] a first aspect, the invention provides circuitry for performing a convolutional Neural Network (CNN) circuitry comprising:[0036] a first aspect, the invention provides stochastic to consecutive edge modulation (CEM) converter comprising:[0037] a first counter configured to generate a first pulse width modulated signal based on the number of high bits in a first frame of a received stochastic signal;[0038] a second counter configured to generate a second pulse width modulated signal based on the number of high bits in a second frame of the received stochastic signal; and[0039] a selector configured to select the first pulse width modulated signal as a first frame of a CEM output signal and to invert the second pulse width modulated signal in time to generate a second frame of the CEM output signal.
Innovation Solution
The circuitry includes multiplexer circuitry to output a time division multiplexed signal based on unary coded input signals, integrated and encoded using vector quantizer and integrator circuitry, and optimized by consecutive edge modulation for efficient MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a multiply-accumulate operation is implemented in stochastic computing using traditional methods, then the multiplication can be performed with a single AND gate, but the accumulation of products becomes complicated and increases circuit complexity
Solution Approach 1:
The patent replaces traditional digital accumulation mechanisms with a stochastic computing approach using AND gates and bitstream processing. The accumulation is performed by stochastically selecting and combining product bitstreams through probability-based operations rather than deterministic addition circuits, thereby maintaining simplicity while achieving the accumulation function.
Solution Approach 2:
The patent changes the parameter domain from deterministic binary values to stochastic probabilities. By representing data as bitstreams with probabilistic content (where the probability of a '1' represents the value), the system transforms complex arithmetic operations into simpler probabilistic operations that can be performed with basic logic gates.
2Measurement precision
If more bits are examined at the output of the AND gate to improve multiplication accuracy, then the precision increases, but the computation time and processing complexity increase
Solution Approach 1:
The patent employs periodic sampling of the bitstream output at regular intervals rather than continuous examination. By sampling at optimized periods that capture sufficient statistical information, the system achieves accurate results without the need to process every bit, thereby reducing computation time while maintaining precision.
Solution Approach 2:
The patent examines only a partial subset of the bitstream output rather than the entire sequence. By selecting and processing a strategically chosen portion of the bits (excessive enough to ensure accuracy but not the full amount), the system achieves the required precision with reduced computational overhead and faster processing.
Data Source
AI summary
The present disclosure relates to circuitry for performing a multiply-accumulate (MAC) operation. The circuitry comprises a first multiplexer having a plurality of inputs for receiving a plurality of unary-coded input signals representing operands of the MAC operation and an output for outputting a multiplexer output signal representing a result of the MAC operation and a first vector quantizer configured to receive a plurality of weighting signals, each representing a proportion of a computation time period for which a respective one of the unary-coded input signals should be selected by the multiplexer and to output a first selector signal to the multiplexer to cause the multiplexer to select each of the input signals in accordance with the plurality of weighting signals.