Unary Sorting Networks Using Time-Encoded Signals
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Solution Overview
Problem
Conventional sorting networks face challenges in efficiency, area, and power consumption, particularly in unary processing, due to high latency and energy requirements, and are susceptible to noise, with binary representations being complex and prone to errors.
Innovation Solution
The implementation of time-encoded data signals using pulse-width modulated (PWM) signals and unary bit streams, which encode numerical values in duty cycles, allowing for simpler and smaller circuitry, and the use of low-cost analog-to-time converters to process data in the unary domain, reducing latency and energy consumption while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional binary sorting networks are used, then sorting capability is achieved, but area and power consumption are high
Solution Approach 1:
The patent replaces conventional binary digital logic circuits with stochastic computing circuits that process probability data. This substitution fundamentally changes the computational approach from deterministic binary operations to probabilistic operations, enabling simpler circuit implementations that achieve the same sorting function with reduced area and power consumption
Solution Approach 2:
The patent changes the data representation parameter from binary format to stochastic probability format. By representing data as probability values in the [0, 1] interval rather than binary numbers, the sorting network can use simpler comparison and swap operations that require fewer logic gates and less circuitry
2Use of energy by stationary object
If conventional binary sorting networks are used, then sorting capability is achieved, but power consumption is high
Solution Approach 1:
The patent replaces energy-intensive binary logic operations with lower-power stochastic computing operations. The stochastic circuits process probability data using simpler logic that consumes less power, while the probabilistic nature of the computation provides inherent noise tolerance that compensates for the reduced circuit complexity
3Device complexity
If unary processing is used, then circuit simplicity is achieved, but latency increases
Solution Approach 1:
The patent employs periodic clocking and synchronized operation in the stochastic sorting network. By using regular periodic operations and pipeline stages, the network manages the processing time required for unary/stochastic operations while maintaining circuit simplicity. The periodic structure allows for optimized timing that reduces overall latency despite the inherent time requirements of probabilistic computation
4Reliability
If stochastic computing is used, then noise tolerance is improved, but data representation complexity increases
Solution Approach 1:
The patent changes the fundamental parameter of data representation from binary digits to probability values. By representing data as probabilities in the [0, 1] interval that can be processed stochastically, the system achieves noise tolerance through the inherent robustness of probabilistic computation, while the data representation remains conceptually simple despite the different mathematical domain
Data Source
AI summary
Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.