Unbalanced Memory Die Stack Layout for Coplanar Package Routing
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Solution Overview
Problem
As semiconductor memory packages increase in storage capacity and decrease in size, the routing of electrical signals between bond wires and the controller becomes more complicated, often leading to wasted space and decreased storage capacity when rearranging memory dies to address routing issues.
Innovation Solution
A semiconductor memory package design featuring unbalanced die stacks, where one stack includes a controller and a greater number of memory dies than the other, with both stacks having coplanar upper surfaces to maximize storage capacity without increasing package size, optimizing routing and reducing waste space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory dies are rearranged to address routing issues, then routing complexity is reduced, but storage capacity decreases due to wasted space
Solution Approach 1:
The patent applies asymmetry by implementing unbalanced die stacks where one stack contains more memory dies than the other. This asymmetric configuration allows the package to accommodate irregular routing paths while maximizing the use of available space, thereby maintaining high storage capacity while addressing routing complexity issues.
Solution Approach 2:
The patent transitions from a traditional balanced two-dimensional layout to a three-dimensional stacked configuration with unbalanced die stacks. This dimensional change allows memory dies to be arranged vertically in stacks of different heights, enabling optimized routing paths through the substrate while maximizing storage capacity without wasting space.
2Quantity of substance
If more memory dies are integrated to increase storage capacity, then storage capacity increases, but routing complexity increases
Solution Approach 1:
The patent segments the memory dies into two separate unbalanced stacks rather than using a single large array. This segmentation divides the routing complexity into two manageable groups, allowing each stack to be routed independently to the controller, thereby increasing storage capacity while controlling routing complexity through modular organization.
Solution Approach 2:
By organizing memory dies into vertical stacks rather than a flat two-dimensional array, the patent adds a vertical dimension to the layout. This allows more memory dies to be integrated within the same footprint while the stacked configuration naturally groups connection points, simplifying the routing paths to the controller compared to a distributed two-dimensional layout.
3Area of stationary object
If package size is decreased to reduce form factor, then package size decreases, but routing complexity increases
Solution Approach 1:
The patent moves from a two-dimensional planar arrangement to a three-dimensional stacked configuration. This allows the package footprint to be minimized while accommodating more memory dies vertically. The stacked architecture naturally consolidates connection points, which simplifies routing paths within the reduced package size compared to trying to route numerous dies in a compressed two-dimensional layout.
Solution Approach 2:
The patent implements a nested structure where memory dies are stacked vertically one on top of another, with each die nested within the vertical space occupied by the package. This nesting approach maximizes space utilization within the reduced package footprint while the vertical stacking consolidates I/O connections, thereby reducing routing complexity despite the compact form factor.
Data Source
AI summary
A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The substrate includes a top layer and a bottom layer. The first stack of memory dies is electrically coupled to the top layer of the substrate and includes a controller and a first number of memory dies. The second stack of memory dies is electrically coupled to the top layer of the substrate and includes a second number of memory dies greater than the first number of memory dies. An upper surface of the first stack of memory dies and an upper surface of the second stack of memory dies are substantially coplanar.