Unbalanced Multiplexer Timing for Low-Voltage Scan Flip-Flops
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Solution Overview
Problem
Current scan test technologies for semiconductor chips face challenges in testing at low voltages, particularly in reducing power consumption while maintaining stability and accuracy.
Innovation Solution
The development of an unbalanced multiplexer and scan flip-flop designs that incorporate distinct delay characteristics for different transmission paths, utilizing cascode structures and transistor configurations to manage signal transmission based on selection signals, allowing for stable testing at low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional scan test technology is used, then testing can be performed, but power consumption increases and stability at low voltage deteriorates
Solution Approach 1:
The multiplexer is segmented into two separate transmission circuits: a first transmission circuit for data signals and a second transmission circuit for scan signals. Each circuit has its own pull-up and pull-down circuits, allowing independent optimization of power consumption and signal integrity for each function, thereby enabling low-voltage operation while maintaining testing stability.
Solution Approach 2:
Different delay characteristics are applied locally to different transmission paths. The first transmission circuit is designed with one delay characteristic optimized for data signals, while the second transmission circuit is designed with a different delay characteristic optimized for scan signals. This local differentiation allows each path to operate efficiently at low voltage without compromising overall system reliability.
2Measurement precision
If balanced multiplexer design is used, then circuit simplicity is maintained, but signal timing accuracy deteriorates due to inability to differentiate between data and scan signals
Solution Approach 1:
The multiplexer is divided into two independent transmission circuits, each handling specific signal types (data or scan). This segmentation allows precise control of timing characteristics for each signal type, improving measurement precision while keeping each individual circuit relatively simple.
Solution Approach 2:
The first and second transmission circuits are designed with asymmetric delay characteristics. The first pull-up circuit and second pull-up circuit have different configurations, as do the pull-down circuits. This intentional asymmetry enables differentiated timing control for data versus scan signals, achieving high timing accuracy without requiring complex additional control logic.
3Speed
If transmission delay is reduced, then signal speed increases, but timing differentiation between data and scan signals deteriorates
Solution Approach 1:
Each transmission circuit is given its own optimized delay characteristic tailored to its specific function. The first transmission circuit's delay is optimized for data signal speed requirements, while the second transmission circuit's delay is optimized for scan signal timing requirements. This local optimization allows both signals to travel at high speeds while maintaining their timing differentiation.
Solution Approach 2:
The circuit design allows dynamic control of signal transmission through the selection signal that controls the pull-up and pull-down circuits. This dynamic control enables the circuit to adaptively manage timing characteristics for different signal types, maintaining both high speed and precise timing differentiation.
Data Source
AI summary
An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.