Uncacheable Memory Cache Policies for Coherence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Maintaining cache coherence across both cacheable and uncacheable regions of the memory address space in integrated circuits is challenging, leading to issues with stale data and inconsistent updates in multiprocessor systems.
Innovation Solution
A processor architecture that divides the address space into cacheable and uncacheable regions, using a multi-level cache hierarchy to keep uncacheable loads and stores coherent with cacheable data, where uncacheable loads are restricted to a portion of the L2 cache and uncacheable stores are treated as write-through, no-write-allocate by the L1 cache, with buffers in the core interface unit gathering data for writing to the L2 cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uncacheable memory requests are processed through the cache hierarchy, then data coherence is improved, but cache complexity increases
Solution Approach 1:
The cache is segmented into separate ways or sets dedicated to uncacheable loads, physically isolating uncacheable data from cacheable data. This segmentation allows the cache to handle uncacheable requests without compromising the coherence of cacheable regions, while maintaining simpler coherence protocols for each segment.
Solution Approach 2:
A buffer in the core interface unit acts as an intermediary for uncacheable stores, gathering data before writing to the L2 cache. This intermediary mechanism simplifies the coherence management by providing a controlled interface between uncacheable store operations and the cache hierarchy, reducing the complexity of direct cache integration.
2Loss of energy
If uncacheable loads are cached in L2 cache, then bandwidth requirements are reduced, but stale data issues worsen
Solution Approach 1:
The L2 cache is segmented to include specific ways or sets allocated exclusively for uncacheable loads. This segmentation allows uncacheable data to be cached for bandwidth efficiency while maintaining clear distinction from cacheable data, preventing stale data issues through physical separation and dedicated storage regions.
3Productivity
If write operations are delayed in cache before updating main memory, then cache performance is improved, but coherence maintenance becomes more difficult
Solution Approach 1:
The cache coherence protocol is segmented to handle uncacheable stores differently from cacheable stores. Uncacheable stores follow a simplified write-through path with direct memory updates, while cacheable stores use delayed writeback. This segmentation allows high-performance writeback for cacheable data while maintaining simple coherence for uncacheable data.
Solution Approach 2:
Instead of delaying writes for uncacheable stores like cacheable stores, the system inverts the approach by immediately writing uncacheable stores through to memory (write-through), while allowing cacheable stores to be delayed. This inversion simplifies coherence management for uncacheable data while maintaining performance for cacheable data.
Data Source
AI summary
Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit. Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.