3D Memory Interconnect Structure With Under-Array Bit Line Decoding
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high density and small size, which are essential for advanced applications, as traditional two-dimensional circuits are limited in terms of power consumption, memory cell density, and efficiency.
Innovation Solution
The development of a three-dimensional (3D) memory structure with a multi-level memory cell array and interconnect structure, featuring gate-all-around (GAA) transistors and nanowire or nanosheet channels, allows for increased memory cell density and efficient interconnects through a staircase configuration of bit and source lines, enabling higher bandwidth and lower cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional circuits are used, then manufacturing process is simpler, but memory cell density is limited and power consumption is higher
Solution Approach 1:
The patent transitions from traditional two-dimensional planar circuits to three-dimensional stacked architectures by vertically stacking multiple memory cell layers and interconnect tiers. This dimensional change enables significantly higher memory cell density within the same footprint area while managing complexity through systematic layering and modular construction approaches
2Quantity of substance
If memory cell size is reduced to increase density, then capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory structure into multiple discrete stacked layers, each containing memory cells of manageable size. This segmentation allows standard manufacturing processes to maintain precision while achieving high overall density through vertical multiplication of layers rather than requiring extremely small individual cell dimensions
3Quantity of substance
If three-dimensional stacked structure is implemented, then memory cell density increases, but interconnect routing complexity increases
Solution Approach 1:
The patent merges bit lines and source lines into combined interconnect structures that serve multiple memory cell layers simultaneously. This merging approach reduces the total number of separate interconnect routes needed compared to fully independent routing for each layer, thereby reducing overall routing complexity while maintaining high density
Solution Approach 2:
The interconnect structures are designed with multi-functionality to serve multiple purposes: bit lines connect to bit line decoders, source lines connect to source line decoders, and the same interconnect tiers support multiple memory cell layers. This universal design reduces routing complexity by eliminating redundant dedicated connections
Data Source
AI summary
Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.