Under-Array Memory Interconnect Layout for Relaxed Pitch Scaling
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Solution Overview
Problem
Conventional semiconductor devices face challenges in interconnect structure design for accessing and operating memory device cells, particularly in scaling down memory device cell design, which affects integration and complexity in processing and manufacturing.
Innovation Solution
The implementation of a peripheral circuit under memory array (PUA) configuration with a multi-layer interconnect (MLI) system that includes metal lines and vias surrounded by dielectric materials, allowing for improved interconnect routing between the peripheral circuit and memory cell array, enabling vertical stacking of memory cells and relaxing interconnect pitch requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory device cell design is scaled down to increase capacity, then production efficiency increases and costs decrease, but interconnect structure complexity increases and manufacturing complexity increases
Solution Approach 1:
The patent implements a peripheral circuit under array (PUA) configuration where peripheral circuits are positioned beneath the memory cell array in a vertical stacking arrangement. This three-dimensional integration approach moves the interconnect problem from a two-dimensional planar layout to a vertical dimension, allowing simultaneous achievement of high density and simplified interconnect routing through vertical vias and stacked layers.
Solution Approach 2:
The patent divides the semiconductor device into distinct functional layers: a first substrate containing peripheral circuits, a second substrate containing memory cell arrays, and intermediate interconnect layers. This segmentation separates the complex interconnect routing into manageable modular components, with each layer handling specific functions, thereby reducing overall manufacturing complexity while maintaining high integration.
2Adaptability or versatility
If peripheral devices are integrated with memory cell arrays, then integration improves and density increases, but interconnect routing complexity and manufacturing difficulty increase
Solution Approach 1:
The PUA configuration stacks the memory cell array vertically above the peripheral circuits, utilizing the vertical dimension to achieve integration without increasing planar footprint. This vertical stacking enables high integration while maintaining simpler interconnect routing through aligned vias and reduced lateral interconnect lengths, thereby easing manufacturing compared to planar integration approaches.
Solution Approach 2:
The patent introduces intermediate interconnect layers and structures positioned between the peripheral circuits on the first substrate and the memory cell arrays on the second substrate. These intermediary elements facilitate signal and power transmission while isolating the two functional blocks, enabling integrated operation with reduced manufacturing complexity by providing buffer zones and simplified routing paths.
3Ease of manufacture
If conventional interconnect structures are used with scaled-down memory cells, then manufacturing processes remain simple, but interconnect pitch requirements become excessively tight and scalability degrades
Solution Approach 1:
By transitioning to vertical stacking with the PUA configuration, the patent relaxes lateral interconnect pitch requirements. The vertical vias and stacked architecture allow sufficient lateral spacing between interconnect elements while achieving high density through vertical multiplication, thereby maintaining manufacturing simplicity with relaxed precision tolerances compared to planar scaling.
Solution Approach 2:
The patent changes the fundamental geometric parameters of the interconnect structure by moving from lateral routing to vertical routing. This parameter change transforms the pitch constraint from a lateral dimension to a vertical dimension, where the pitch can be larger and easier to manufacture, while the effective interconnect density increases through the vertical stacking factor.
Data Source
AI summary
A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.