Semiconductor Package Under Bump Interconnection Layer Trenches
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high reliability, miniaturization, and increased integration density due to limitations in packaging design and manufacturing methods.
Innovation Solution
The semiconductor package design incorporates a redistribution substrate with an under bump interconnection layer, electronic devices, and solder bumps, featuring a passivation layer with trenches that inhibit underfill layer flow and enhance interface contact, thereby improving reliability and allowing for miniaturization and higher integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package size is reduced to meet miniaturization demands, then integration density improves, but reliability deteriorates due to increased stress and thermal issues
Solution Approach 1:
The package structure is segmented into multiple functional layers including substrate, under bump interconnection layer, passivation layer, and solder bump layer. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall package integrity and reliability despite reduced size
Solution Approach 2:
The patent transitions from planar 2D layout to 3D vertical stacking by adding the under bump interconnection layer between the substrate and solder bumps. This dimensional change enables increased integration density without proportionally increasing package footprint, thereby maintaining reliability in smaller packages
2Productivity
If integration density is increased to improve functionality, then device capability improves, but manufacturing complexity increases
Solution Approach 1:
The under bump interconnection layer is formed on the substrate before mounting the solder bumps. This preliminary action simplifies subsequent assembly steps and enables higher integration density by pre-establishing the interconnection architecture, thereby reducing overall manufacturing complexity despite increased integration requirements
Solution Approach 2:
The passivation layer is selectively applied to specific regions where needed for insulation and protection, rather than uniformly across the entire surface. This localized approach enables higher integration density in critical areas while simplifying manufacturing in less critical regions
3Area of stationary object
If solder bumps are placed closer to electronic devices to reduce pitch, then integration density improves, but delamination risk increases
Solution Approach 1:
The under bump interconnection layer acts as an intermediary between the substrate and solder bumps, providing mechanical support and stress distribution. This intermediary structure enables closer placement of solder bumps while maintaining delamination resistance, thereby achieving higher integration density without sacrificing reliability
Solution Approach 2:
The passivation layer is applied beforehand to protect the under bump interconnection layer and conductive patterns from environmental damage and mechanical stress. This protective cushioning enables closer spacing of solder bumps while maintaining reliability by preventing stress-induced delamination
Data Source
AI summary
A semiconductor package includes a redistribution substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip mounted on the first surface of the redistribution substrate, an under bump interconnection layer on the second surface of the redistribution substrate, an electronic device mounted on the under bump interconnection layer, and a solder bump disposed on the under bump interconnection layer and horizontally spaced apart from the electronic device. The under bump interconnection layer includes conductive patterns respectively connected to the electronic device and the solder bump, and a passivation layer covering the conductive patterns. The passivation layer includes a plurality of trenches disposed between the electronic device and the solder bump.