Under-Bump Pattern Geometry for Reliable Semiconductor Packaging

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Solution Overview

Problem

Current semiconductor packages face challenges in reliability and durability due to issues with the under-bump pattern design, which affects the electrical connections and the overall performance of the semiconductor chip.

Innovation Solution

The semiconductor package incorporates a redistribution substrate with an under-bump pattern, an under-bump seed pattern, and dielectric layers, where the under-bump pattern has a central and edge region design with specific angles and thicknesses, and the under-bump seed pattern covers the sidewall to enhance protection and connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the under-bump pattern is designed with a conventional structure, then the fabrication process is simple, but the reliability and durability of the semiconductor package are reduced

Engineering Contradiction:
Improvereliability and durabilityVSAvoidunder-bump pattern structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The under-bump pattern is designed with different thicknesses at different locations: the first thickness at the first region (edge) and the second thickness at the second region (center), where the first thickness is greater than the second thickness. This local variation in thickness provides enhanced protection at the edges where impurities are more likely to enter, while maintaining structural integrity overall, thereby improving reliability without excessive complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The under-bump pattern transitions from a conventional two-dimensional planar structure to a three-dimensional structure with varying thickness and an inclined surface. The angle of inclination is controlled to be between 45 degrees and 60 degrees, creating a wedge-like profile that provides both mechanical strength and protection against external impurities, resolving the contradiction between reliability improvement and structural complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If the under-bump pattern has a higher thickness, then the protection against external impurities is improved, but the fabrication precision requirements increase

Engineering Contradiction:
Improveprotection against external impuritiesVSAvoidthickness control
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The thickness of the under-bump pattern is optimized within specific ranges: the first thickness at the edge region is controlled between 5-15 micrometers, and the second thickness at the center region is controlled between 3-10 micrometers. These parameter specifications provide sufficient protection against external impurities while maintaining manufacturability and avoiding excessive precision requirements that would complicate the fabrication process

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If the angle between the bottom surface and sidewall is increased, then the protection capability is improved, but the fabrication complexity increases

Engineering Contradiction:
Improveprotection capabilityVSAvoidfabrication process
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The angle between the bottom surface and the inclined surface of the under-bump pattern is controlled to be between 45 degrees and 60 degrees. This angular parameter optimization provides effective protection against external impurities by creating a geometry that resists contaminant penetration, while remaining within the capabilities of standard fabrication processes and avoiding excessive complexity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11948872B2Semiconductor package and method of fabricating the same
Publication Date: 2024.04.02 SAMSUNG ELECTRONICS CO LTD
  • US11948872B2 patent drawing
  • US11948872B2 patent drawing
  • US11948872B2 patent drawing

AI summary

Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.