Under-Bump Metal Recess Structure for Drop-Resistant Semiconductor Packages
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Solution Overview
Problem
Semiconductor devices and packages face challenges in drop test characteristics and impact resistance due to their increasing vulnerability to external impacts as they become smaller and thinner.
Innovation Solution
Incorporating a substrate with a conductive layer, an insulating layer featuring recesses or trenches, and an under-bump metal layer that fills these recesses or trenches, which helps in reducing crack propagation and enhancing the device's ability to withstand external forces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices become smaller and thinner, then device size is reduced, but impact resistance deteriorates
Solution Approach 1:
The patent applies beforehand cushioning by forming a recess in the insulating layer beneath the solder bump before the bump is attached. This recess creates a cushioning space that absorbs impact energy during drop tests, preventing direct transmission of shock forces to the substrate and protecting the semiconductor device from damage despite its small and thin dimensions.
Solution Approach 2:
The patent applies segmentation by dividing the insulating layer into two distinct regions: a recess portion with reduced thickness beneath the solder bump, and a non-recess portion with normal thickness in surrounding areas. This segmented structure allows the device to have both impact resistance at critical locations and overall compactness, resolving the contradiction between small size and impact resistance.
2Strength
If a recess is formed in the insulating layer, then impact resistance is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming the recess only in specific localized areas beneath solder bumps where impact forces are concentrated, rather than modifying the entire insulating layer. This localized modification improves impact resistance at critical points while maintaining simplicity in non-critical areas, thus improving impact resistance without proportionally increasing overall device complexity.
3Reliability
If the recess is deeper, then crack propagation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by optimizing the recess depth to a specific range (10-50 μm) that provides sufficient crack propagation resistance while remaining manufacturable with standard precision capabilities. By carefully selecting and controlling the recess depth parameter within this optimal range, the patent achieves both improved reliability against crack propagation and feasibility with conventional manufacturing precision.
Data Source
AI summary
Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.