Semiconductor Package Layout With Under-Chip Capacitor Nesting

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Solution Overview

Problem

The existing semiconductor packaging technologies face challenges in miniaturization due to the need for multiple capacitors to filter high-frequency noise and stabilize voltage, which increases the package size and limits the effectiveness of noise filtering and voltage stabilization.

Innovation Solution

The capacitor is positioned under the chips, reducing the vertical distance and encapsulating it within the semiconductor package on the same layer as the connection structure, maintaining package size while enhancing noise filtering and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple capacitors are arranged on the substrate to increase capacitance, then the voltage stabilization and noise filtering effect is improved, but the package size increases

Engineering Contradiction:

Improvevoltage stabilization and noise filtering effectVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from horizontal arrangement of capacitors on the substrate to vertical stacking beneath the chip. By changing the spatial dimension from 2D (horizontal) to 3D (vertical), the capacitor array occupies space underneath the chip rather than expanding the package footprint, thus improving noise filtering capability without increasing package size.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent nests multiple capacitors vertically beneath the chip structure. The capacitors are stacked in layers under the chip, with connection structures extending upward to connect to the chip's power and ground pins. This nesting approach allows multiple capacitors to occupy a compact vertical space, providing high capacitance in a small footprint.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Ease of manufacture

If capacitors are placed far from chips horizontally, then the package layout is simplified, but the noise filtering and voltage stabilization effect is reduced

Engineering Contradiction:

Improvepackage layoutVSAvoidnoise filtering and voltage stabilization effect

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent resolves the layout complexity by moving capacitors to the vertical dimension beneath the chip. Instead of placing capacitors horizontally adjacent to the chip, they are stacked vertically under the chip with connection structures extending upward. This dimensional change simplifies the horizontal layout while maintaining close proximity for effective noise filtering.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260005111A1Semiconductor packaging method, semiconductor package and electronic device

Publication Date: 2026.01.01 SHANGHAI YIBU SEMICON CO LTD

AI summary

A semiconductor packaging method, which utilizes a connection structure and an interconnection device to realize electrical connections between semiconductor devices and a power supply and the interconnection between the semiconductor devices. A capacitor is provided and is located on at least one side of the connection structure, and on at least one side of the interconnection device. Packaging the capacitor inside the semiconductor package and arranging it in a same layer as the connection structure and the interconnection device maintains the size of the semiconductor package, is conducive to miniaturization, shortens the distance between the capacitor and the semiconductor devices, and improving the effect of the capacitor in filtering high-frequency noise in the resulting circuit, which is conducive to improving the working stability of the semiconductor devices.