Under Device Interconnect Routing for Microelectronic Cell Size Reduction
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Solution Overview
Problem
Interconnect routing within microelectronic devices limits the miniaturization of cell layouts due to design and placement constraints, hindering advancements in processor performance as device dimensions shrink.
Innovation Solution
The solution involves forming microelectronic structures by creating a device layer in a first substrate and a routing layer in a second substrate, then coupling them with a bonded intermediate layer, allowing routing layers to be located underneath the device layer, thereby reducing cell size and enabling more efficient power and signal delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If interconnect routing is placed within the device layer, then signal and power delivery is achieved, but cell size cannot be reduced further due to routing space constraints
Solution Approach 1:
The patent applies dimensionality change by moving interconnect routing from the traditional planar layer (within the device layer) to a vertical dimension (underneath the device layer). This is achieved through through-silicon vias (TSVs) that penetrate the device layer, allowing routing layers to be positioned in the z-dimension below the active device region. This spatial reconfiguration resolves the contradiction by decoupling routing space from device footprint, enabling cell size reduction while maintaining routing functionality.
2Productivity
If device dimensions are shrunk for higher processor performance, then processing capability improves, but interconnect routing becomes a limiting factor
Solution Approach 1:
The patent applies segmentation by dividing the interconnect structure into distinct functional segments: device layer (containing active devices), through-silicon via layers (providing vertical interconnection), and separate routing layers (providing signal and power distribution). This segmentation allows each layer to be independently optimized - devices can be miniaturized for performance while routing layers underneath provide adequate space for interconnect design, thus resolving the contradiction between processor performance and routing constraints.
3Area of moving object
If routing layers are relocated underneath device elements, then cell size is reduced by up to 40%, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the through-silicon vias and establishing the vertical interconnect structure before completing the device layer fabrication. The TSVs are created early in the process, allowing subsequent routing layers to be deposited and patterned underneath the device elements without requiring complex post-processing steps. This sequencing of operations simplifies manufacturing despite the three-dimensional architecture, enabling cell size reduction while managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces cell size by up to 40% by relocating power, ground, and signal routing layers below the device elements, facilitating smaller device layouts and improved performance.
Implementation Method 1
coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate
Data Source
AI summary
Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.