Two-Tier Trench Isolation Under Epitaxy for Leakage and Capacitance
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges with current leakage and capacitance issues in nano-FET transistors due to the contact between source/drain regions and the semiconductor material, which affect the integration density and performance of electronic components.
Innovation Solution
The implementation of a low-k insulation material at the bottom of recesses before forming source/drain regions, combined with an upper insulation layer to form a trench isolation structure, reduces current leakage and capacitance by creating a more effective isolation between the source/drain regions and the semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain regions are formed in direct contact with semiconductor material to maintain device structure, then device structural integrity is maintained, but current leakage and parasitic capacitance increase
Solution Approach 1:
The isolation structure is segmented into two distinct layers: a lower isolation layer positioned at the bottom of the recess to provide electrical isolation and reduce current leakage, and an upper isolation layer deposited over the lower layer to provide additional isolation and protection. This segmentation allows each layer to perform its specific function optimally without interfering with device structural integrity.
Solution Approach 2:
The lower isolation layer acts as an intermediary material inserted between the source/drain regions and the semiconductor material. This intermediary layer prevents direct electrical contact that would cause current leakage and parasitic capacitance, while the upper isolation layer provides additional intermediary protection during subsequent processing steps.
2Reliability
If low-k insulation material is deposited at the bottom of recesses to reduce parasitic capacitance, then parasitic capacitance decreases, but the low-k material becomes vulnerable to damage during subsequent processing
Solution Approach 1:
The lower isolation layer made of low-k insulation material is deposited first at the bottom of the recesses before any subsequent processing steps. This preliminary placement ensures that the parasitic capacitance reduction is achieved early in the manufacturing process, and the protective upper isolation layer is then added to preserve this benefit throughout subsequent processing.
Solution Approach 2:
The upper isolation layer serves as a protective cushion deposited over the vulnerable low-k material of the lower isolation layer. This beforehand protection prevents damage to the low-k material during subsequent processing steps such as etching, cleaning, or deposition, ensuring the parasitic capacitance reduction benefit is maintained through manufacturing.
3Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but current leakage and capacitance issues worsen
Solution Approach 1:
Instead of attempting to solve current leakage in the lateral dimension by further reducing feature size, the solution moves to the vertical dimension by introducing a multi-layer isolation structure. The lower isolation layer is positioned at the bottom of recesses, and the upper isolation layer is deposited over it, creating vertical separation that effectively blocks current leakage paths without compromising the lateral integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density of electronic components by minimizing parasitic capacitance and current leakage, while providing a robust isolation structure that protects the low-k insulation material from damage during subsequent processing steps.
Implementation Method 1
depositing a first insulating film in the recess, the first insulating film having a first k value; depositing a second insulating film in the recess over the first insulating film
Data Source
AI summary
Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.