Integrated Power Amplifier With Under-IC Load Inductor
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Solution Overview
Problem
Existing power amplifiers in wireless communication devices face challenges in achieving low loss and high efficiency due to the high inductance requirements of load inductors, which affect the power added efficiency (PAE) and in-band impedance.
Innovation Solution
The implementation of a load inductor under an IC die with a flip-chip configuration, where the IC die is mounted directly over the load inductor on the IC package, reducing loss and increasing the quality factor (Q) by minimizing interconnect trace length and using solder balls for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the load inductor is implemented with conventional interconnect traces on the IC package, then the power amplifier can be assembled, but the loss increases and quality factor decreases due to long trace lengths
Solution Approach 1:
The load inductor is moved from the planar IC package surface to the vertical dimension by placing it underneath the IC die. This three-dimensional arrangement eliminates long interconnect traces by directly coupling the inductor to the power amplifier transistor through the flip-chip substrate, thereby reducing energy loss.
Solution Approach 2:
The load inductor is nested underneath the IC die, with the die mounted directly over the inductor on the IC package. This nested configuration minimizes the distance between components and eliminates the need for separate interconnect traces, reducing loss and improving quality factor.
2Reliability
If the load inductor is placed far from the power amplifier transistor, then the IC package layout is simplified, but the quality factor decreases due to increased parasitic effects
Solution Approach 1:
By transitioning from a planar layout to a three-dimensional vertical arrangement, the inductor is positioned directly underneath the transistor. This eliminates the trade-off between proximity and package area, as the vertical stacking allows close coupling without increasing the planar footprint.
3Productivity
If conventional packaging is used with separate inductor and amplifier components, then manufacturing is simpler, but the overall device area increases and efficiency decreases
Solution Approach 1:
The load inductor and power amplifier transistor are merged into a single integrated structure where the inductor is positioned directly underneath the die. This integration eliminates separate components and interconnects, reducing both device area and energy loss, thereby improving power added efficiency.
Data Source
AI summary
A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.