Under-Transistor Power Connections for Semiconductor Routing Density
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Solution Overview
Problem
The semiconductor industry faces challenges in designing power supplies and signal lines due to the reduction of routing areas and the complexity of integrating multi-gate electrode transistors, which existing source electrode/drain electrode contact structures are not adequately addressing.
Innovation Solution
A method for manufacturing a semiconductor structure with power connecting structures formed directly under transistors, involving a stop layer structure, patterned stop layers, and a series of etching and deposition processes to create open slots and fill them with power connecting structures, allowing for improved routing and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power connecting structures are directly formed under transistors to improve routing efficiency, then routing area complexity is reduced, but manufacturing process complexity increases
Solution Approach 1:
The substrate is divided into a first substrate part (containing transistors and power connecting structures) and a second substrate part (removed in thinning process). This segmentation allows selective formation of power connecting structures under transistors while maintaining manufacturing feasibility through staged processing.
Solution Approach 2:
The stop layer structure is formed in advance within the semiconductor substrate before the thinning process. This preliminary action defines the depth limit for subsequent etching operations, ensuring that power connecting structures are formed at the correct position under transistors without penetrating through the entire substrate.
Solution Approach 3:
Power connecting structures are formed in the vertical dimension (under transistors through substrate thinning) rather than only in the planar routing dimension. This dimensional change reduces routing area complexity by utilizing the depth direction for power connections.
2Productivity
If multi-gate electrode transistors are implemented to reduce device size and increase packaging density, then integration density is improved, but design of power supplies and signal lines becomes more complex
Solution Approach 1:
Power connecting structures extend vertically through the substrate thickness to contact source and drain electrodes of multi-gate transistors from below. This vertical connection approach simplifies power supply design by providing direct access to transistor terminals without complex lateral routing.
Solution Approach 2:
Instead of routing power lines laterally from the sides of multi-gate transistors, the power connecting structures approach the transistor terminals from the bottom (opposite direction), penetrating through the substrate to establish contacts with source and drain electrodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by allowing power connecting structures to be directly connected to the source and drain electrodes of transistors, reducing the complexity of routing areas and improving the flexibility of the manufacturing process.
Implementation Method 1
forming an electroplating seed layer to cover the protecting layer and the conductive layer
Data Source
AI summary
A method for manufacturing a semiconductor structure with power connecting structures under transistors comprises: forming a stop layer structure in a semiconductor substrate to divide the semiconductor substrate into a first substrate part and a second substrate part; forming a plurality of stop portions in the first substrate part and in proximity to an active surface; arranging the transistor elements on the active surface, the contact portions of the transistor elements corresponding to the stop portions; removing the second substrate part and the stop layer structure; forming a first patterned mask layer with first patterned openings on a bottom surface of the first substrate part, the first patterned openings corresponding to the stop portions; forming through open slots in the first substrate part and exposing the contact portions via the open slots; forming a protecting layer to cover side walls of the open slots; forming a conductive layer to cover the contacts; and forming the power connecting structures in the open slots. The method has flexibility and can improve the device performance.