Undercut Isolation Regions for SOI FET Shorts Prevention
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Solution Overview
Problem
In silicon-on-insulator (SOI) devices, determining an appropriate buried oxide (BOX) thickness is challenging due to increased capacitance between source/drain regions and the bottom substrate as BOX thickness decreases, leading to unpredictable FET device performance and potential shorts between source/drain contacts and the bottom substrate.
Innovation Solution
The formation of undercut isolation regions by etching trenches through the top SOI layer and BOX into the bottom substrate, filled with an insulating material, which isolates the source/drain regions from the bottom substrate and prevents shorts by creating a thick dielectric at the edge of active regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the BOX layer thickness is decreased, then the FET device speed increases due to reduced capacitance, but the risk of shorts between source/drain contacts and bottom substrate increases
Solution Approach 1:
The isolation structure extends horizontally underneath the source/drain regions by creating an undercut trench that laterally etches into the bottom substrate beneath the BOX layer. This horizontal extension in the planar dimension provides additional isolation distance without increasing vertical BOX thickness, thereby preventing shorts while maintaining fast device speed.
Solution Approach 2:
The isolation structure is divided into two functional segments: a vertical portion extending through the BOX layer and a horizontal undercut portion extending laterally underneath the source/drain regions. This segmentation allows the vertical segment to provide primary electrical isolation while the horizontal segment provides additional safety margin against shorts, enabling thin BOX design.
2Reliability
If the BOX layer thickness is increased, then floating channel regions are prevented, but the capacitance between source/drain regions and bottom substrate increases leading to increased circuit loading
Solution Approach 1:
Instead of increasing vertical BOX thickness to prevent floating channels, the invention extends isolation horizontally by creating an undercut trench that laterally etches into the bottom substrate underneath the source/drain regions. This horizontal extension provides additional isolation distance without increasing vertical thickness, thereby preventing floating channels while maintaining low capacitance and reduced circuit loading.
3Reliability
If a thin BOX layer is used in UTBB devices, then floating channel regions are prevented, but shorts between source/drain contacts and bottom substrate may occur
Solution Approach 1:
The isolation structure creates a horizontal undercut trench that laterally etches into the bottom substrate underneath the source/drain regions, extending the isolation distance in the planar dimension. This allows the use of thin BOX layers to prevent floating channels while the horizontal undercut portion provides additional protection against shorts by increasing the lateral distance that charge carriers must traverse to reach the bottom substrate.
4Speed
If the BOX layer thickness is decreased, then faster FET devices are achieved, but capacitance coupling to the bottom substrate increases
Solution Approach 1:
The invention compensates for increased capacitance coupling from thin BOX layers by extending isolation horizontally through creating an undercut trench that laterally etches into the bottom substrate underneath the source/drain regions. This horizontal extension increases the effective isolation distance without increasing vertical thickness, thereby maintaining low capacitance coupling while enabling fast device speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents shorts between source/drain contacts and the bottom substrate, stabilizing FET device performance by providing a thick insulator at the edge of active regions and reducing capacitance fluctuations.
Implementation Method 1
The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region
Data Source
AI summary
A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.