Undercut Source/Drain Regions in Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices, such as DRAM and eDRAM, face challenges with high junction leakage current leading to reduced data retention time and increased costs due to inefficient source/drain region designs.
Innovation Solution
The method involves forming semiconductor memory devices with undercut source/drain regions using a substrate with elongated fins, hard masks, and fill material, creating vertical cavities and spacers to define T-shaped fins, and isolating the source/drain regions with an upper surface of the isolation material below the fin surface, enhancing electrical resistance and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain region designs are used in DRAM memory devices, then manufacturing is simpler, but junction leakage current is high leading to reduced data retention time
Solution Approach 1:
The patent introduces a third dimension by creating undercut source/drain regions that extend laterally beneath the gate structure. This dimensional change allows the source/drain regions to be positioned in a configuration that increases electrical resistance and reduces leakage current paths, directly addressing the high junction leakage problem while improving data retention time
Solution Approach 2:
The patent applies different structural qualities to different regions: the source/drain regions have an undercut configuration with increased lateral extent beneath the gate, while the channel region maintains its conventional vertical fin structure. This localized structural modification optimizes the source/drain regions for reduced leakage without affecting the channel's transistor switching characteristics
2Object-generated harmful factors
If undercut source/drain regions with isolation material below fin surface are formed, then junction leakage current is reduced, but device structure and manufacturing process become more complex
Solution Approach 1:
The patent performs preliminary actions by forming the undercut source/drain regions and positioning the isolation material below the fin surface before final gate formation. This sequencing allows the complex structural elements to be established early in the process, enabling subsequent steps to build upon this foundation rather than attempting to add complexity later
Solution Approach 2:
The patent segments the fin structure into distinct functional regions: the visible fin portion extending above the isolation material, and the undercut source/drain regions extending laterally beneath the gate. This segmentation allows each region to be optimized independently for its specific function while managing overall structural complexity
Data Source
AI summary
A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.