Undercut Trench Sidewalls Suppress Dislocation Propagation
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Solution Overview
Problem
In semiconductor devices, the reduction of threading dislocation density is challenging, especially when growing highly crystalline channel layers over amorphous interlayers, as existing techniques like Aspect Ratio Trapping require high aspect ratios and increased procedural complexity, and dislocations from seed layers with different lattice constants hinder device performance.
Innovation Solution
A semiconductor device with a trench structure having an undercut configuration is developed, where the heterolayer is formed within the trench with non-vertical sidewalls, reducing threading dislocation propagation by configuring the trench such that its top width is narrower than the bottom width, and the sidewalls intersect at an angle that terminates dislocation propagation, thereby minimizing dislocation density without the need for a buffer layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Aspect Ratio Trapping technique is used to reduce dislocation density, then threading dislocation propagation is suppressed, but procedural complexity increases and high aspect ratio is required
Solution Approach 1:
The patent changes the geometric parameters of the trench structure by forming non-vertical sidewalls with specific angles (α and β) relative to the substrate surface. By controlling the sidewall angles to satisfy specific relationships (α + β > 90° and α > 45°), the patent achieves dislocation suppression without requiring high aspect ratios, thus reducing procedural complexity while maintaining reliability
Solution Approach 2:
The patent introduces asymmetry in the trench sidewall configuration by forming sidewalls with different angles (α and β) rather than symmetric vertical walls. This asymmetric geometry creates specific stress distributions and dislocation propagation paths that effectively suppress threading dislocations while allowing for lower aspect ratios compared to conventional symmetric ART structures
2Adaptability or versatility
If seed layer with different lattice constant is used, then heteroepitaxial growth is enabled, but dislocations are formed at the interface
Solution Approach 1:
The patent applies local quality by creating a specific geometric configuration (undercut structure with non-vertical sidewalls) at the interface region between the seed layer and substrate. This localized geometric modification affects dislocation propagation specifically at the critical interface area, allowing heteroepitaxial growth to proceed while suppressing dislocation formation at the interface through the controlled sidewall angles
3Reliability
If buffer layer is added to reduce dislocation density, then channel layer quality is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent extracts and eliminates the buffer layer from the conventional heteroepitaxial growth structure by using the undercut trench geometry with non-vertical sidewalls as the dislocation suppression mechanism instead. This removes the need for an additional buffer layer, reducing device complexity and manufacturing steps while maintaining channel layer quality through the geometric control of dislocation propagation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dislocation density in the seed layer, allowing for higher-quality channel layer growth with reduced procedural complexity and cost, particularly in Monolithic 3D and FINFET structures, by suppressing threading dislocation propagation and eliminating the need for a buffer layer.
Implementation Method 1
when the seed layer is grown from a material having a different lattice constant from Si, dislocations are formed. The dislocations include misfit dislocations at the interface between the seed layer and the Si substrate
Implementation Method 2
threading dislocations extending upward from the underlying substrate... threading dislocations propagating from a seed layer to be formed in the trench into an overlying channel layer
Data Source
AI summary
Embodiments relate to a semiconductor device including a trench with undercut structure including a substrate made of a first material; an insulation layer formed on an upper surface of the substrate; at least one trench penetrating the insulation layer toward the substrate; and at least one seed layer formed in the trench, the seed layer made of a second material which is different from the first material, and a method for manufacturing the same.