Undercutted Gate Structure for DRAM Packing Density
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Solution Overview
Problem
The scaling down of transistors in DRAM cells leads to increased short-channel effects and subthreshold leakage, degrading performance due to reduced channel length, which hampers the packing density and overall performance of Dynamic Random Access Memory devices.
Innovation Solution
A semiconductor device with a semiconductor substrate featuring a shallow trench isolation structure, a protrusion structure with an undercut, and a gate structure that crosses over the protrusion, where the source and drain semiconductor features are positioned at opposite sides of the gate, enhancing the contact area and control over electron flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the transistor channel length is reduced to increase packing density, then the packing density is improved, but short-channel effects and subthreshold leakage increase, degrading transistor performance
Solution Approach 1:
The gate structure is extended vertically into the substrate, transitioning from a planar 2D configuration to a 3D configuration. This vertical extension increases the gate's control area over the channel without reducing the channel length, thereby maintaining transistor performance while enabling continued scaling for higher packing density.
Solution Approach 2:
The gate structure is embedded within the substrate, with the gate extending from the surface into the substrate volume. This nesting approach allows the gate to occupy three-dimensional space within the substrate, increasing the effective control area without adding lateral footprint, thus resolving the contradiction between packing density and transistor performance.
2Length of moving object
If the standard channel length is reduced, then the transistor size is reduced, but short-channel effects become more pronounced, increasing subthreshold leakage
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional configuration by extending vertically into the substrate. This dimensional change increases the gate's control area without reducing the channel length, thereby maintaining control over subthreshold leakage while enabling smaller transistor footprints.
Solution Approach 2:
The gate structure parameters are changed by extending its length vertically into the substrate. This parameter change increases the gate control area, providing better control over the channel and reducing subthreshold leakage effects even as the transistor footprint is reduced.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.