Semiconductor Package Underfill Barrier Layout for Void Containment
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Solution Overview
Problem
The occurrence of voids in underfill materials within semiconductor packages reduces the reliability of the underfill materials and electronic products, as they can cause defects and structural instability.
Innovation Solution
A semiconductor package design that includes a package substrate with a dam structure and an ejection prevention barrier, where the dam structure surrounds the sub-package and the ejection prevention barrier is positioned on one side, spaced apart from the sub-package with the dam structure in between, to prevent void formation and underfill material impurities from contaminating peripheral devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an underfill material is applied to fill the gap between the semiconductor chip and mounting substrate, then the protection of connection bumps and stress relief are improved, but void formation occurs which reduces reliability
Solution Approach 1:
The patent introduces an ejection prevention barrier as an intermediary structure between the underfill material and the peripheral devices. This barrier prevents voids and impurities within the underfill material from reaching and contaminating the peripheral devices, thereby maintaining reliability despite the presence of voids in the underfill material itself.
Solution Approach 2:
The patent segments the package structure by introducing the ejection prevention barrier that divides the space into a protected region (where peripheral devices are located) and an underfill region. This segmentation isolates the harmful voids within the underfill material from the peripheral devices, allowing the underfill to perform its protective function while preventing harm to other components.
2Reliability
If the underfill material is applied extensively to surround the sub-package, then the protection and stress relief are improved, but the underfill impurities can reach and contaminate peripheral devices
Solution Approach 1:
The ejection prevention barrier acts as a protective intermediary that blocks the path of underfill impurities. It allows the underfill material to be applied extensively for optimal protection and stress relief while preventing the impurities from reaching the peripheral devices, thus resolving the contamination issue.
Solution Approach 2:
The patent extracts or removes the harmful aspect (impurity contamination) from the underfill material application process by introducing the ejection prevention barrier. This barrier selectively allows the beneficial functions of the underfill material (protection and stress relief) to operate while blocking the harmful effect (impurity ejection onto peripheral devices).
Data Source
AI summary
A semiconductor package includes a package substrate, a sub-package arranged on the package substrate, an underfill material layer arranged between the package substrate and the sub-package, a dam structure spaced apart from the sub-package, on the package substrate, and extending to surround the underfill material layer, and an ejection prevention barrier arranged on one side of the sub-package, on the package substrate, and spaced apart from the sub-package in a first horizontal direction with the dam structure therebetween, wherein a top surface of the dam structure has a first vertical level, and a top surface of the ejection prevention barrier has a second vertical level higher than the first vertical level.